Artificial neural networks, as physical systems, are implemented through hardware substrates that realize interconnected processing units and weighted connections using electronic, optical, or neuromorphic architectures. In conventional digital hardware, they are instantiated as configurations of logic gates, memory arrays, and interconnects on CPUs, GPUs, or specialized accelerators (e.g., TPUs), where weights reside in volatile or non-volatile memory and computation is executed via parallel multiply-accumulate operations. Emerging neuromorphic and analog implementations encode synaptic weights in device conductances (e.g., memristors, phase-change materials) and exploit device physics for in-memory computation, enabling high spatiotemporal parallelism, low-latency signal propagation, and energy-efficient approximation of neural operations in a physically embedded network topology.
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