Highly durable silicon carbide (SiC) power semiconductor TED-MOS for energy saving in electric vehicle motors

September 4, 2018, Hitachi
Credit: Hitachi

Hitachi, Ltd. today announced the development of an original energy saving power semiconductor structure, TED-MOS, using next-generation silicon carbide (SiC) material that contributes to saving energy in electric vehicles (EV). This power semiconductor is a new device using a fin-structured trench MOSFET based on the conventional DMOS-FET, a SiC transistor of power semiconductor. Using this new device, an energy saving of 50 percent was confirmed as the structure reduces the electric field strength, an index of durability, by 40 percent and resistance by 25 percent compared to the conventional DMOS-FET. Hitachi intends to apply this device in motor drive inverters which are a core component of EVs to increase energy efficiency. Furthermore, by utilizing this technology not only in EVs but also in a range of electrical transducers used in societal infrastructure systems, Hitachi hopes to contribute to efforts to reduce global warming and the realization of a low-carbon society.

With the anticipated increase in global energy demand, targets to reduce environmental load are being set through initiatives such as the SDGs and COP21 to realize a sustainable society. As the adoption of EVs is also expected to increase dramatically, reducing EV consumption is considered critical, Thus, the use of power semiconductors using SiC as the semiconductor material which can deliver significant energy savings for inverters, is attracting much attention. One issue, however, is that in SiC power semiconductor, unlike silicon (Si) devices, the varies greatly depending on the crystal plane. Although trench SiC MOSFET (Fig. 1(2)) has been proposed as a means to facilitate the flow of electric current on the crystal plane at a lower resistance in comparison to the conventional DMOS-FET (Fig. 1(1)) structure, as electric fields easily concentrate at the edges of the trench on the base plane, it was difficult to simultaneously achieve high durability.

To address this challenge, Hitachi developed an original fin-structure trench DMOS-FET "TED-MOS" that achieved both a reduction in resistance with the smaller trench pitch and high durability with lower electric fields for industrial applications at high voltage (3.3 kV), and presented these results in May 2018 at the International Symposium on Power Semiconductor Devices and ICs (ISPSD) in Chicago, U.S.A..

This time, Hitachi has enhanced the "TED-MOS" for EV inverters as they require higher current density at a lower voltage (1.2 kV) (Fig. 1(3)). The "field relaxation layer (FRL)" was developed to reduce the electric field strength extensively, where the PN junction to relax the applied voltage forms in the center of the device structure. In addition, the "current spreading layer (CSL)" was developed to reduce the resistance in the n-JFET region, which serves to form the electric current path connecting the sides of the fin-like trenches as low-resistance crystal planes and the n-JFET region. As a result, "TED-MOS" simultaneously achieves both a smaller electric field strength and lower resistance in SiC power semiconductors.

The benefits of this technology development was verified using a prototype device. It was found that the "TED-MOS" reduced the electric field strength by 40 percent and resistance by 25 percent in comparison to the conventional DMOS-FET while maintaining the rated voltage of 1.2kV required for the motor drive in EVs. Furthermore, the modified structure mentioned above also improved the switching speeds between ON/OFF of the power , and as a result, loss in the electric current due to this switching operation was also reduced by 50 percent.

Going forward, Hitachi will contribute to the prevention of global warming and the realization of a low-carbon society by applying this technology to various electrical transducers, not only in EVs but also in various societal infrastructure systems.

Explore further: Researchers quantify factors for reducing power semiconductor resistance by two-thirds

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