Researchers develop multilevel memory for consumer electronics

November 27, 2014, Trinity College Dublin
A titanium oxide nanowire acts as both a diode and a memristor

Researchers at AMBER, the Science Foundation Ireland funded materials science centre, and the School of Chemistry, Trinity College Dublin, have developed a solution to increase the speed interaction between processor and memory in computers and other electronic devices.

Instead of each cell storing just a single piece or 'bit' of information, the team - led by Professor John Boland with researchers Curtis O'Kelly and Jessamyn Fairfield has developed a multilevel memory in which it is possible to programme a number of stored bits into a single cell. Multilevel memory increases communication speed by reducing the number of memory cells.

Whether your favorite app runs on a mobile phone or a supercomputer, performance no longer depends solely on the brain power or so-called processor speed. To function, the processor has to communicate efficiently with memory on the chip. The properties of the metal wires connecting the processor and memory provide a fundamental speed limit.

Professor John Boland, AMBER, explained: "Processors and memory communicate using the clunky language of binary code. Conventional on-chip memory stores information as '1's' and '0's', which reflects the presence or absence of charge at the memory location. For example, 2014 in binary language requires 11 cells of memory. It take time for the computer to access such a large number of cells and so the overall performance is impaired. The new process reduces the number of cells required."

The scheme proposed by the AMBER researchers operates on a different principle; the resistance to charge flow, known as resistive memory which ultimately leads to more streamlined processing with fewer cells but with each having multiple memory levels. A particular advantage of the new approach is that it is possible to arbitrarily tune the number of memory levels within each cell.

"The discovery opens up a host of possibilities for the consumer leading to smaller, cheaper and faster electronics. Having demonstrated six memory levels per cell, we believe the technology can be developed to display even more memory levels per cell. A memory language with greater density can increase the efficiency and speed of desktop and mobile technology by reducing the number of memory locations," said Professor Boland.

"Further research will be focused on integrating this technology with existing industry fabrication capabilities, so that society can continue to reap the benefits with new and improved technology," Professor Boland concluded.

Explore further: Improving flash memory: New molecular storage devices could bridge memory gap

More information: The paper, A Single Nanoscale Junction with Programmable Multilevel Memory is available at: pubs.acs.org/doi/abs/10.1021/nn505139m

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EyeNStein
not rated yet Nov 27, 2014
Good, Multi level Memristors. Like Flash memory has been using for years in MLC cells.
It could improve memory density and reduce price for memristors when they eventually come to market.
Though the density gain is at the expense of read latency and reliability (and probably wear levelling?).
The functional loss caused by introducing wear levelling problems to memristors may not be worth it.
Selena
Nov 27, 2014
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EyeNStein
not rated yet Nov 27, 2014
All digital devices are analogue at heart. Just with a defined threshold where 0 becomes 1 at each point in a circuit; and enough gain is added to accentuate that transition to successive circuit elements.
In the case of a 2 bit multi level cell 3 different thresholds define the transitions from 00 to 01 to 10 and to 11 (binary). In flash cells the analogue quantity is electron charge stored. In Memristors its the crystalline resistance of a cell element.
As more levels are used (doubling for each additional bit) the uncertainty of the thresholds increases due to noise, leakage, manufacturing variances and wear/usage cycling until cells becomes fabrication rejects or are later unable to reliably recover data.
alfie_null
not rated yet Nov 28, 2014
I'm curious about the usual reliability related aspects of this technology. The number of discrete levels is a trade off; more levels mean more errors. How stable over time? Read/write cycles? How much space devoted to error correction?
EyeNStein
not rated yet Nov 28, 2014
@Alfie: As we haven't even seen single level cells on the market yet, and they were first developed years ago, they currently have manufacturing reliability issues. So that sort of information will remain commercially confidential. Even when they launch we will have to read between the lines: about device parity correction (if any) and spare data blocks on the die. We may also get the vaguest hints on process yield in news stories.

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