Elpida begins sample shipments of DDR3 SDRAM (x32) based on TSV stacking technology

June 28, 2011

Elpida Memory today announced that it has begun sample shipments of the industry's first DDR3 SDRAM (x32-bit I/O configuration) made using TSV (Through Silicon Via) stacking technology. The sample is a low-power 8-gigabit (1-gigabyte) DDR3 SDRAM assembled in a single package that consists of four 2-gigabit DDR3 SDRAMs fitted to a single interface chip using TSV.

TSV is three-dimensional stack , which involves stacking together multiple chips vertically through with metal-filled via holes in the SI die. Compared with the existing connection method of wire bonding multiple chips, TSV greatly reduces the length of wires in the semiconductor design to enable faster speeds, lower power consumption, smaller package size and other important chip function advantages.

Elpida began developing TSV, now recognized as a key next-generation chip technology, in 2004 based on a grant program hosted by the New Energy and Industrial Technology Development Organization (NEDO), a research endeavor founded by the Japanese government. Since then Elpida has continued to develop TSV technology. In 2009 it successfully developed the industry's first TSV DRAM based on stacking together eight 1-gigabit DDR3 SDRAMs.

In the case of notebook PCs, Elpida believes that trial use of its 8-gigabit TSV DRAM samples will demonstrate that compared with systems that use SO-DIMM (Small-outline DIMM), operating power can be reduced by 20% and by 50%. Also, the chip mounting area can be reduced by 70%, the chip height can be decreased and the DIMM socket can be eliminated. The new TSV DRAM will be presented as an eco-friendly DRAM that can contribute greater energy savings and enable thin , tablet PCs and other mobile computing products experiencing rapid market growth to become even smaller, thinner and lighter.

Explore further: Elpida Completes Development of Cu-TSV (Through Silicon Via) Multi-Layer 8-Gigabit DRAM

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