Intel, Micron Sample 3-Bit-Per-Cell NAND Flash Memory on 25-Nanometer Process Technology

Aug 18, 2010
25nm TLC Die

Intel and Micron Technology today announced the delivery of 3-bit-per-cell (3bpc) NAND flash memory on 25-nanometer process technology, producing the industry’s highest capacity, smallest NAND device.

The companies have sent initial product samples to select customers. Intel and Micron expect to be in full production by the end of the year.

The new 64-gigabit (Gb) 3bpc on 25nm offers improved cost efficiencies and higher storage capacity for the competitive USB, SD (Secure Digital) flash card and consumer electronics markets. Flash memory is primarily used to store data, photos and other multimedia for use in capturing and transferring data between computing and digital devices such as digital cameras, portable media players, digital camcorders and all types of personal computers. These markets are under constant pressure to provide higher capacities at low prices.

Designed by the IM Flash Technologies (IMFT) NAND flash joint venture, the 64-Gb, or 8 gigabyte (GB), 25nm lithography stores three bits of information per cell, rather than the traditional one bit (single-level cell) or two bits (multi-level cell). The industry also refers to 3bpc as triple-level cell (TLC.)

The device is more than 20 percent smaller than the same capacity of Intel and Micron’s 25nm MLC, which is currently the smallest single 8GB device in production today. Small form-factor is especially important for consumer end-product flash cards given their intrinsic compact design. The die measures 131mm2 and comes in an industry-standard TSOP package.

“With January’s introduction of the industry’s smallest die size at 25nm, quickly followed by the move to 3-bit-per-cell on 25nm, we continue to gain momentum and offer customers a compelling set of leadership products,” said Tom Rampone, Intel vice president and general manager of Intel NAND Solutions Group. “ plans to use the design and manufacturing leadership of IMFT to deliver higher-density, cost-competitive products to our customers based on the new 8GB TLC 25nm NAND device.”

Explore further: Renesas announces SRAM using leading-edge 16 nm FinFET for automotive information systems

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User comments : 3

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Buyck
3 / 5 (1) Aug 19, 2010
This is the beginning of a huge revolution on memory capacity! We gonna see even smaller nodes in the coming years 15nm, 11nm or even smaller!
1 TB on a USB-stick comes possible.
simulus
5 / 5 (1) Aug 19, 2010
we mustnt get carried away. The circuits outside the memory array are not shrinking but growing and they are not benefiting from the advanced nodes.
plasma_guy
5 / 5 (1) Aug 26, 2010
The capacity is increased 3x, but the number of write cycles is decreased 2 orders of magnitude (~1000 instead of 100000), so in the end I have to spend much more on replacements. Rather just use SLC.

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