At today's 2011 IEEE International Electron Devices Meeting (IEDM), imec presents the worlds smallest, fully-functional HfO2-based Resistive RAM (RRAM) cell, with an area of less than 10x10nm². The new cell shows potential to meet the major requirements for future device-level nonvolatile memory. RRAM is an emerging technology for nonvolatile memory, a candidate to replace NAND Flash technology in the scaling race to sub-10nm memories.
Current charge storage based Flash memory technologies are believed to face scaling limitations beyond 18nm. To overcome these, a variety of innovative cell and memory concepts are investigated worldwide. One of the most promising memory concepts is the resistive RAM or RRAM. It is based on the electronic switching of a resistor element material between two stable (low/high) resistive states. The major strengths of RRAM technology are its potential density and speed.
Imecs RRAM cell features a novel Hf/HfOx resistive element stack. It couples a cell area of less than 10x10nm2 with an excellent reliability (endurance of more than 109cycles). The cell has fast nanosecond-range on/off switching times at low-voltages. It has a large resistive window (>50) and shows no closure of the on/off window after functioning at 200°C for 30 hours. The device even remained operating failure-free functioning for 30 hours with a thermal stress of 250°C. The switching energy per bit is below 0.1pJ, and AC operating voltages are well below 3V. With these characteristics, imecs cell meets the major requirements for device-level nonvolatile memory.
In addition, imec has also further clarified the impact of film crystallinity on the operation of RRAM cells, especially with a view on further scaling. It also sheds light on the role of the cap layer and on the switching mechanisms.
These results were obtained in cooperation with imecs key partners in its core CMOS programs Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, Hynix, Fujitsu and Sony.
Explore further: Imec achieves breakthroughs in enabling future DRAM and RRAM