Toshiba develops silicon nanowire transistor for 16nm generation and beyond

Jun 15, 2010
Figure 1: Structure of a silicon nanowire transistor

(PhysOrg.com) -- Toshiba Corporation today announced that it has developed a breakthrough technology for a nanowire transistor, a major candidate for a 3D structure transistor for system LSI in the 16nm generation and beyond.

The company has achieved a 1mA/μm on-current, the world's highest level for a nanowire transistor, by reducing parasitic resistance and improving the on-current level by 75%. This is a major step towards practical application of nanowire . This achievement will be presented at the 2010 Symposium on VLSI Technology in Hawaii, on June 17.

When the size of current planar transistors scales smaller, current leakage between the source and the drain at its off-stage (off-leakage) will become a critical problem in securing circuit reliability. To overcome this, transistors with a 3D structure, including nanowire transistors, are being investigated as candidates for future generations of devices.

The silicon nanowire transistor can suppress off-leakage and achieve further short-channel operation, because its thin wire-shaped silicon channel (nanowire channel) is effectively controlled by the surrounding gate. However, parasitic resistance in the nanowire-shaped source/drain, especially in the region under the gate sidewall, degrades the on-current.

overcame this problem by optimizing gate fabrication and significantly reducing the thickness of the gate sidewall, from 30nm to 10nm. Low parasitic resistance was realized by epitaxial silicon growth on the source/drain with a thin gate sidewall, which leads to a 40% increase in on-current.

Figure 2: Comparison with the previous work

The company also achieved a further 25% increase in current performance by changing the direction of the silicon nanowire channel from the <110> to <100> plane direction. Utilizing these technologies, Toshiba has demonstrated an industry-leading on-current level of 1mA/μm, when the off-current is 100nA/μm, a 75% increase in the on-current at the same off-current condition.

This work was partly supported by New Energy and Industrial Technology Development Organization (NEDO) 's Development of Nanoelectronic Device Technology.

Explore further: A bump circuit with flexible tuning ability that uses 500 times less power

Related Stories

Intel Researchers Improve Tri-Gate Transistor

Jun 13, 2006

Intel Corporation researchers today disclosed they have developed new technology designed to enable next era in energy-efficient performance. Intel's research and development involving new types of transistors ...

IMEC to create solutions for sub-45nm CMOS scaling

Jun 17, 2005

Together with its CMOS core partners, IMEC will announce several research breakthroughs on new gate-stack technologies and multiple-gate FET (MuGFET) devices at the 2005 Symposium on VLSI Technology. A combination of advances ...

Recommended for you

Myo armband and smartglasses set for deskless workplace

52 minutes ago

Thalmic Labs, Canada-based makers of the Myo armband, has announced the integration of Myo with smartglasses, with the partnership help of a number of companies pairing the Myo with their products. The gesture-control ...

Indonesian capital threatens to ban Uber car app

1 hour ago

The Indonesian capital is threatening to shut down controversial smartphone car-hailing service Uber due to licensing issues a week after it officially launched in the city, an official said Wednesday.

Apple's stock bounces back to hit a new high (Update)

2 hours ago

Apple's stock touched a new high Wednesday, reflecting investors' renewed faith in CEO Tim Cook's ability to outwit the competition and expand the technological hit factory built by the late Steve Jobs.

User comments : 0