Intel, Micron Achieve Industry’s Most Efficient NAND Product Using 3-Bit-Per-Cell Technology

Aug 11, 2009

Intel Corporation and Micron Technology today announced the development of a new 3-bit-per-cell (3bpc) multi-level cell (MLC) NAND technology, leveraging their award-winning 34-nanometer NAND process. The chips are typically used in consumer storage devices such as flash cards and USB drives, where high density and cost-efficiency are paramount.

Designed and manufactured by IM Flash Technologies (IMFT), their joint venture, the new 3bpc NAND technology produces the industry’s smallest and most cost-effective 32-gigabit (Gb) chip that is currently available on the market. The 32Gb 3bpc NAND chip is 126mm².

Micron is currently sampling and will be in in the fourth quarter 2009. With the companies’ continuing to focus on the next process shrink, 3bpc NAND technology is an important piece of their product strategy and is an effective approach in serving key market segments.

“We see 3bpc NAND technology as an important piece of our roadmap,” said Brian Shirley, vice president of Micron’s memory group. “We also continue to move forward on further shrinks in NAND that will provide our customers with a world-leading portfolio of products for many years to come. Today’s announcement further highlights that Micron and Intel have made great strides in 34-nanometer NAND, and we look forward to introducing our 2xnm technology later this year.”

Source: Intel (news : web)

Explore further: Renesas announces SRAM using leading-edge 16 nm FinFET for automotive information systems

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User comments : 2

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sender
not rated yet Aug 12, 2009
This reminds me of octal to hex hardware translation mechanisms. Using BCD translations of hex and oct can be performed by simple hardware spacing.
gongii
5 / 5 (2) Sep 18, 2009
Flash will have hard time matching HDD Tb-scale storage already available today.

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