IBM introduces new graphene transistor

Apr 11, 2011 by Deborah Braconnier report
Image credit: Nature, doi:10.1038/nature09979

(PhysOrg.com) -- In a report published in Nature, Yu-ming Lin and Phaedon Avoris, IBM researchers, have announced the development of a new graphene transistor which is smaller and faster than the one they introduced in February of 2010. This new transistor has a cut-off frequency of 155 GHz, compared to the 100 GHz previous transistor.

Graphene is a flat sheet of carbon which is one atom thick and has the ability to conduct at extremely fast speeds. It is quickly on its way to replace the traditional silicon as the top electronic material for faster .

Graphene devices have been made previously by placing the graphene sheet on top of an insulating substrate, such as silicon dioxide. However, this substrate can degrade the of the graphene. However, the team of researchers has found a solution to minimize that.

A diamond-like carbon is placed as the top layer of the substrate on a silicon wafer. The carbon is non-polar dielectric and does not trap or scatter charges as much as the alone. This new graphene transistor, due to the diamond-like carbon, shows excellent stability in temperature changes, including extremely cold temperatures like that in space.

These new high-frequency transistors are being targeted to applications primarily in communications such as mobile phones, internet, and radar.

The manufacturing of these new transistors can be accomplished utilizing technologies already in place for standard silicon devices, which means commercial production of these transistors could begin at any time.

The transistor development was part of an ongoing research project IBM is doing for the U.S. Department of Defense’s DARPA (Defense Advanced Research Projects Agency) program. The military is looking to this research to help in the development of high-performance radio frequency transistors.

Explore further: Engineers discover new method to determine surface properties at the nanoscale

More information: High-frequency, scaled graphene transistors on diamond-like carbon, Nature, 472, 74–78 (07 April 2011) doi:10.1038/nature09979

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User comments : 22

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SmartK8
1.4 / 5 (9) Apr 11, 2011
Nice, the next generation of performance is almost here. Waiting for a countermove from Microsoft.
rynox
not rated yet Apr 11, 2011
It is nice to see a real application for graphene so quickly. One question, and this is just my own ignorance because I don't know a ton about the subject, but is graphene waste an environmental concern?
Quantum_Conundrum
1 / 5 (3) Apr 11, 2011
It is nice to see a real application for graphene so quickly. One question, and this is just my own ignorance because I don't know a ton about the subject, but is graphene waste an environmental concern?


I don't think anyone knows enough about graphene to say just yet.
dirk_bruere
4.5 / 5 (8) Apr 11, 2011
very unlikely to be a graphene environmental problem given that it occurs naturally in pencils
mahvin
not rated yet Apr 11, 2011
Is there a performance increase over currently used chips? The article did not mention it.
kaasinees
3.7 / 5 (6) Apr 11, 2011
Is there a performance increase over currently used chips? The article did not mention it.

Even if the transistor is larger than traditional transistors, its transision speed is enormous, uses less energy and creates less heat. The number of transistors needed to be of comparable speed of nowadays chips is much less.

but is graphene waste an environmental concern

I think you mean nanotubes? They are feared to have the same effect as asbestos... but its not certain yet.

Nice, the next generation of performance is almost here. Waiting for a countermove from Microsoft.

Don't you mean Global Foundries and other CPU/GPU bakers?
Microsoft does not bother with transistors, neither does intel or amd or nvidia etc, they design architectures and layout.

-- and the usual nonsense crap spouted by QC, take ur meds man.
Quantum_Conundrum
2 / 5 (4) Apr 11, 2011
Is there a performance increase over currently used chips? The article did not mention it.


Let's say each transistor is 155ghz, as the article says.

Now let's say you have a processor which needs to process instructions and data, and we'll call it a 64-bit processor.

Now not every instruction is the same. Some instructions are straightforward and don't even require individual calculations, while other instructions require things like adding, subtracting, and multiplication, etc.

Pure math instructions are the slowest, because you don't know what one bit in your register should be until you'd done the math for the previous bit. Sort of like 7 + 8 = 15, you had to carry a 1, and if you were a machine, you wouldn't know that till you actually added the "ones" place. (ok, so they work in binary...)

Anyway, it depends on the operation.
PhilippJFR
1 / 5 (1) Apr 11, 2011
What no one seems to realize with regards to higher frequency chips is that you'll never get the information, which is to be processed, to the chip fast enough to even come close to making use of each clock cycle.
Quantum_Conundrum
2.6 / 5 (5) Apr 11, 2011
So for example, you could expect a processor or network card or other device using graphene transistors to PROBABLY have a net clock speed of around 15ghz, maybe a bit more than that.

From the diagram, it looks like the transistor there is probably a 40nm gate, which is not that much bigger than existing 32nm gate transistors.

So that would be about 50% larger area (or reversing the reference, you could fit 2/3rds as many 40nm gates in the same area as 32nm gates.)

Now 2/3rds of transistors, but anywhere from 4 to maybe 10 times faster clock speed, he, you do the math....

As a multiplier of existing computer logic operations...
Low end:

(2/3) * 4 = 8/3 = 2 + 2/3

high end:

(2/3) * 10 = 20/3 = 6 + 2/3

And then, I assume, they'd eventually be able to miniaturize graphen as small or smaller than silicon technology, if for no reason other than the fact Carbon atoms are slightly smaller radius than Silicon...
Quantum_Conundrum
2.6 / 5 (5) Apr 11, 2011
What no one seems to realize with regards to higher frequency chips is that you'll never get the information, which is to be processed, to the chip fast enough to even come close to making use of each clock cycle.


Not true. There are several techniques for doing it, including racetrack memory for faster reads from the secondary storage.

Then there is optical buses, which will avoid the heat waste and resistance of electrical buses, and should even end up with less signal delay, AND avoid the problem of cross-talk between nano-wires.

The reason L1 through L3 cache were invented is to move the most heavily used code fragments into memory on the same chip as the actual processor and registers. This allows for much smaller signal delays.

Once they have optical buses, they will cut signal distances to essentially straight line between devices on the motherboard, instead of the existing wires that have to circumvent one another, reducing signal delay furthe
Quantum_Conundrum
2 / 5 (4) Apr 11, 2011
What no one seems to realize with regards to higher frequency chips is that you'll never get the information, which is to be processed, to the chip fast enough to even come close to making use of each clock cycle.


Ok, and the other thing you fail to realize is they'll eventually have graphene or nanowire RAM which pushes spin charges along circuitry, instead of electrical impulses, which is faster and uses less energy.

So we will eventually see spintronic and optical devices on the motherboard which will solve the signal delay problems and the bus speed problems.

You're also forgetting "hyperthreading".

Let's say you are right, and the processors are so much faster than everything, well, you could design the chipset and entire motherboard to compensate by having multiple redundant input buses to run multiple threads simultaneously from different memory and cache.

So each core might run 4 pipelines, therefore 4 to 8 threads at 15 gigahertz...no down time at all.
PhilippJFR
not rated yet Apr 11, 2011
Thanks, Quantum_Conundrum I retract my statement.
DrDeth
not rated yet Apr 11, 2011
very unlikely to be a graphene environmental problem given that it occurs naturally in pencils


LMAO - 5 stars.
sstritt
3.7 / 5 (3) Apr 11, 2011
very unlikely to be a graphene environmental problem given that it occurs naturally in pencils


LMAO - 5 stars.

LMAO*2- occurs NATURALLY in pencils? Anyway- how ironic that the substance in the lowest tech item is now the highest tech.
sstritt
1 / 5 (1) Apr 12, 2011
@dhughes
I understand that you can get graphene from a pencil, we were laughing at the notion that pencils occurred naturally.
AkiBola
not rated yet Apr 12, 2011
Pure math instructions are the slowest, because you don't know what one bit in your register should be until you'd done the math for the previous bit. Sort of like 7 + 8 = 15, you had to carry a 1, and if you were a machine, you wouldn't know that till you actually added the "ones" place. (ok, so they work in binary...)
Anyway, it depends on the operation.


So which operation will you be getting? Addition can be done with carry lookahead logic, meaning it can be fast. Multiplication, same, just use more transistors and structure it to be as fast as you want it to be. Pipelining is another tool to improve the throughput with some latency cost. I hope you don't work for a chip design company. Unless they need janitors.
alfonz
5 / 5 (1) Apr 12, 2011
I heard that pencils grow wild in Pennsylvania.
sstritt
3 / 5 (2) Apr 12, 2011
I heard that pencils grow wild in Pennsylvania.

I only buy free range #2's
Vendicar_Decarian
1 / 5 (2) Apr 16, 2011
"The reason L1 through L3 cache were invented is to move the most heavily used code fragments into memory on the same chip as the actual processor and registers. This allows for much smaller signal delays." - QC-TardBall

As usual, you have it all wrong QC, and PhilippJFR is perfectly correct in his assertion that without an increase in RAM speed, enhancements in CPU speed won't matter much.

Contrary to your uninformed blather, it is not the distance of the RAM to the CPU - the signal path length - is not a significant impediment to getting data to the CPU.

There are in fact several factors that limit speed.

These factors are.

1. The impedence of the capacitors in the DRAM device during a read.

2. The impedence of the capacitors in the DRAM device during a write.

3. The time needed to perform a logical decode of the address provided by the CPU into Row and Column bit selects.

4. The impedence of the signal path to the CPU.

5. The time needed to refresh the DRAM device when idle
Vendicar_Decarian
1 / 5 (1) Apr 16, 2011
The factors above are placed in order of importance.

These limitations are for DRAM (Dynamic RAM of course). Static RAM can be made faster as there are no refresh requirements and hence delays 1,2 and 5 do not apply.

The problem with Static RAM is that it requires several transistors per bit while DRAM requires only 1. Hence Static RAM (SRAM) is faster but less dense and hence more expensive and more power hungry.

CPU Cash RAM is generally implemented as Static RAM due to its speed advantage. With Static RAM being on the same die as the CPU, delay 4 also vanishes, leaving only the address decoding delay.
Vendicar_Decarian
1 / 5 (1) Apr 16, 2011
In any case, graphine transistors could be exploited for RAM of course, and if implemented as Static RAM would probably negate any need for level 2 caches.

The computational limits of computing are rapidly being reached.

In real terms, there may be a factor of 10 left before the absolute practical end is reached.
ahmedgnz
not rated yet Apr 17, 2011
Good science should always be reported in good grammar. In the fourth paragraph, the last sentence that ends "... including extremely cold temperatures like that in space" should be "like THOSE in space" since the relative pronoun's referent cold temperatures is plural. An article not checked for grammatical errors may often lead the reader to wonder how well its facts might have been checked also.

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