Intel and Micron memory chip tuned to data driven age

Intel and Micron Technology say chips with 3D XPoint technology are a "major breakthrough"
Intel and Micron Technology say chips with 3D XPoint technology are a "major breakthrough"

Intel and Micron Technology on Tuesday unveiled what they touted as a new kind of memory chip that could "revolutionize" computing devices, services and applications.

Intel and Micron, both based in the United States, said chips with 3D XPoint technology, described as a "major breakthrough," were already in production and represented the first new breed of memory since the introduction of NAND flash in 1989.

"This new class of is a revolutionary technology that allows for quick access to enormous data sets and enables entirely new applications," Micron president Mark Adams said in a release.

Non-volatile memory means that data is saved even when power is turned off.

Intel and Micron reasoned that the explosion of connected devices from smartphones and fitness bands to power meters, appliances, cars and more is generating massive amounts of new data that must be stored and analyzed quickly.

The new memory chip technology is as much as 1,000 times faster an more enduring than NAND, a popular non-volatile memory used in computers, and 10 times denser than what is typically used in machine when it comes to packing in data, according to the companies.

"For decades, the industry has searched for ways to reduce the lag time between the processor and data to allow much faster analysis," Intel senior vice president Rob Crooke said.

"This new class of non-volatile memory achieves this goal and brings game-changing performance to and storage solutions."

Examples given of benefits from the technology included shop owners more swiftly identifying fraud patterns in financial transactions; health care researchers analyzing data in real time, and tracking diseases or parsing genetic data.

The 3D XPoint technology could also enhance personal computing in ways such as making social media interactions faster or video games more immersive, the companies said.

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Jul 28, 2015
can you please write a few more technical details?

@verkle: Agreed - a technical/science website should have at least some technical details.
Partly it is that few details are available, but the writer didn't even dig for those.

The micron web site(http://www.micron...chnology ) has a bit more, and their long video has a few technical details from 10 to 14 minutes in, but it is still mostly just marketing.
The Q&Q says products on the market in 2016, cost between NAND flash and DRAM, and 1000x the re-write performance of NAND flash, and 'faster' read speed.

The Intel website only adds that it is 10x denser than DRAM:

But no lithography spec or feature size, no numbers on the read speed comparison, and no die size details on either web site.

Jul 29, 2015
Agreed, this article isn't science journalism, it's a press release aimed at nontechnical readers. This isn't what we come to to read.

I've absorbed fuller articles elsewhere on the net. Interesting fact: it's a transistorless technology. In other words, it sidesteps Moore's Law entirely - instead of doubling transistors every two years and halving the cost, it does away with transistors and does something completely different to speed up computers. The *idea* behind Moore's Law (faster and cheaper over time) is intact and robust, but perhaps it needs to be restated in terms other than transistors.

This nonvolatile memory tech is plenty fast enough to be used in place of dynamic RAM - in fact the distinction between computational memory and storage could vanish altogether. If it makes it to market, computer architectures are going to go through some big changes.

Jul 29, 2015
@Urgelt - yes, this looks like interesting technology.
If it lives up to its promises it will have flash density and non-volatility with near-DRAM speed, endurance, and write granularity, and with scaling should become less expensive to make than flash.

EETimes has a bit more information on it today (http://www.eetime...55aa3231 ), but the information released so far is still short on technical details...

Jul 29, 2015
Yes, RS, details are in short supply. But not as short as's presser would lead us to think.

We know it's a 20 nm process, so there's room for improvement below that. We can see from photographs that the prototype chip appears to be a true 3-D design, something we haven't yet seen make it to market. We know it's transistorless. We know the memory density is higher than NAND/SSD densities and enjoys far superior durability. We know they're talking about read-write rates of 20 GB/sec, roughly - not as good as top-end DRAM (up to about 50 GB/sec), but better than low-end DRAM (9 GB/sec) and an order of magnitude better than NAND/SSD. We know that to take advantage of a storage device of this speed, a new architecture will be required.

And we know that if a computer architecture is properly designed with this storage medium in mind, it's going to be blazingly fast. And non-volatile! There are an awful lot of pluses. It's a big jump forward.

Jul 29, 2015
See: http://www.semate...0Kau.pdf

1e + 6 is the write endurance (slide 24) [From comment in eetimes per @RealScience reference.]

This might be OK for SSD/Flash use. Definitely not good for DRAM.

Jul 29, 2015
winthrom, that's just the first iteration. They'll go to smaller nm processes, refine designs... most important, they'll optimize bus and CPU architectures to work with 3D XPoint storage.

Perhaps they'll keep DRAM in early gen implementations and use 3D XPoint as just faster, more tightly-integrated drive storage. A bit later on, CPUs could access 3D Xpoint directly, along with DRAM, but I suspect OS, CPU and bus designs will have to be modified to make that work.

If the technology keeps getting better, it might one day replace DRAM, but it doesn't have to replace DRAM to be useful in speeding processing, particularly data-intense processing (as with internet server farms). It won't do much for math-intensive computation. But there's an awful lot of data-intensive computing to do, and it'll help enormously with that - if they can bring it to market. Hopefully they can.

In other words, a number of product cycles lie beyond 1st-gen performance characteristics.

Jul 29, 2015
@Urgelt - I must have missed the 20 nm process - thanks.

@winthrom - Intel has not said that this is phase-change memory, and Micron lists it in a separate section from their phase-change products, and intel insists that the new product involved totally new materials. None the less the slides of this new memory do look like phase-change memory, and PCM is a bulk-change resistive memory, so it looks and sounds like PCM. Have you confirmed that it is PCM?

Jul 29, 2015
@RealScience - I have not confirmed this is PCM. Everything is speculation. The commentators on eetimes had the same comments. I did find a 2010 reference to a version of CeRAM


"Correlated Electron Random Access Memory (CeRAM) is a particular transition metal oxide (TMO) based Resistance Random Access Memory (RRAM) that does not involve electroforming and exhibits reliable unipolar resistance switching properties. A physical model of NiO based CeRAM/RRAM is proposed in the present work. The two stable resistance states in NiO are attributed to intrinsic metallic and insulating states of the material, rather than the creation and rupture of filaments. ..."

A breakthrough in this might be the type of variant that gets past the PCM write limitations.

Intel/Micron are mum on what they are actually doing.

@Urgelt - good points if this has no built in write endurance barrier

Jul 29, 2015
"McWilliams, Christopher R. (M.S., Electrical Engineering)
Correlated electron Random Access Memory: Physical Design, Realization, and Characterization
Thesis directed by Prof. Carlos A. Paz de Araujo
The device fabrication process, switching properties and characterization of Correlated
Electron Random Access Memories (CeRAMs) are described herein. Film synthesis techniques,
test pattern process flows, High temperature retention, Cycle dispersion and optimization, Cycle
Fatigue, and switching parameter optimization have been investigated. ... CeRAMs also show exceptional read endurance with no evidence
of fatigue out to 1012 cycles. ..."
The abstract (http://adsabs.har........3X) says that the "default to ON" state of CeRam, a major problem, is fixed.

This may be it (or should be)

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