Going Beyond Moore's Law by Using the Third Dimension

Jan 18, 2010 By Lisa Zyga feature
(A) Illustration of a conductive particle attracted to a disclination line that joins two electrodes at points P and Q. (B) Photograph of a horizontal necklace of particles. The red bar is 30 micrometers long. Image copyright: Fleury, et al. (c)2009 APS.

(PhysOrg.com) -- Scientists have demonstrated a new microwire fabrication technique in which microwires self-assemble themselves in a three-dimensional template made of nematic liquid crystals. Amidst concerns about Moore’s law eventually approaching a limit in two dimensions, the new fabrication method could enable researchers to continue to increase the density of transistors on integrated circuits by making use of the third dimension.

The researchers, Jean-Baptiste Fleury, David Pires, and Yves Galerne of the Institute of Physics and Chemistry of Materials of Strasbourg, in Strasbourg, France, have published their research in a recent issue of .

As the researchers explain, many different processes have been proposed in the past few years for fabricating high-quality nanowires. Generally, in order to connect nanowires to electrodes, researchers must confine them on a two-dimensional substrate and use the for manipulating the connections, often using a computer.

In their new study, the scientists show how to manufacture microwires that self-assemble themselves in a three-dimensional template and then connect themselves to electrodes with an accuracy of a few micrometers. First, the researchers took the two substrates to be connected, and filled the space between them with a nematic liquid crystal, which is the same substance used in many kinds of LCDs. Although the molecules in the liquid are free to move, they align themselves parallel to one another, except along threadlike (defect) lines (“nemato” in Greek means “threadlike”).

Next, the scientists created a defect line in the nematic liquid crystal that runs between electrodes in the two substrates. By rubbing the substrates in three different locations at a specific angle, the researchers produced a programmable disclination (i.e., a topological or defect line). In this area, the molecules cannot orient themselves in any direction, creating a disclination that extends between the two substrates.

In addition to their ability to produce programmable disclinations, another property of nematic liquid crystals is that they attract small objects to the disclinations. This attraction occurs due to interference between the distortion from the disclination and the normal threadlike distortion from particles in the nematic liquid crystal. The interference results in a force on silica particles (which are added to the nematic liquid crystal), dragging them toward the disclination line.

Eventually, enough silica particles become trapped onto the line to form a micronecklace in which the particles are in loose contact with each other. To thoroughly join the particles together, the researchers applied a voltage difference between adjacent particles in order to polymerize monomers in the liquid crystal and eventually to stick the particles to one another. After a few hours, polymerization turned the micronecklace into a cohesive microwire.

“As far as I know, there are no other means, at the moment, able to produce microwires self-connected in 3D on designed ,” Galerne told PhysOrg.com.

The researchers predict that this process can be extended to produce a large number of microwires between substrates simultaneously, which could lead to the development of large-scale three-dimensional integrated circuits. Although the microwires need to be separated from each other by a minimum distance, which presents a physical limitation, the method still has the potential to play a significant role in future electronics applications.

“The escape to the third dimension could clearly open possibilities,” Galerne said. “A simple manner could consist in connecting stacks of 2D . For the moment we are working on a method for producing nanowires of better quality (smoother shape, larger strength, and better conductivity).”

Explore further: Physics professor publishes exact solution to model Big Bang and quark gluon plasma

More information: Jean-Baptiste Fleury, David Pires, and Yves Galerne. “Self-Connected 3D Architecture of Microwires.” Physical Review Letters 103, 267801 (2009).

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Nik_2213
not rated yet Jan 18, 2010
When they come to patent the notion, they may be referred to 'Callahan and the Wheelies' by Stephen Barr...
Sonhouse
5 / 5 (3) Jan 18, 2010
The main problem I see here is present day CPU's and memory chips have significant heat flow problems already, getting as hot as a waffle iron on a per square cm basis. When you go to 3 dimensions, each layer will have to dissipate about the same amount of heat. Now each chip has a huge heat sink hooked up for CPU's and if you had ten layers like that the heat load would be in the kilowatt area. That is a whole other layer of design issues that may prove to be intractable, perhaps limiting the devices to 2 or 3 layers. Even at that, it would be a huge improvement in real estate efficiency but even with only 3 layers you triple the heat load. Big problem I see there.
ArkavianX
5 / 5 (3) Jan 18, 2010
They'd need to add cooling layers in between the transistor/logic layers, much like the heatpipe tech seen in current fan heatsinks.

The Sebeck/Peltier effect would mostly be key to ridding the heat/thermal load, or at least get it out of the chip.
PinkElephant
5 / 5 (5) Jan 18, 2010
Part of the reason modern chips run so hot, is because there's a need to get maximum performance out of each unit area on the chip.

With a 3D chip, you could cut the frequency and/or voltage, so that each layer performs at 1/4 of "normal" computation output (let's say.) By doing this, however, you'll cut heat dissipation down to 1/16 (dissipated power goes roughly as a square of frequency and/or voltage, provided constant capacitance and/or resistance respectively, IIRC.)

So, you can stack 10 such layers, and you still dissipate 30%+ less energy overall than a high-performance flat chip of the same area, yet you provide 2.5 times more calculation capacity.

Now insert some heat guiding layers (carbon nanotubes maybe, or evaporative cooling channels) and you could drive up voltage or frequency without overheating, or use 100 layers instead of 10.

Then, start using synthetic diamond instead of silicon as a substrate...

Methinks Moore's Law will be with us for a while longer... =)
jimbo92107
1 / 5 (1) Jan 18, 2010
"Self-assemble themselves?" Really? Where's your grammar, in the kitchen washing dishes?
dan42day
1 / 5 (1) Jan 20, 2010
Now just imagine what we could do if we discover other dimensions on the nano-scale.
drewgrey
not rated yet Jan 22, 2010
Increasing density is great but what if one dimension was used to connect the tarnsistors in serial like in CPUs and if the third dimension is used to connect those same tansistors in parallel like in GPUs. Could transistors be made to gate in multiple directions?

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