Intel Corporation today disclosed details of its forthcoming Intel Core microarchitecture, a new industry–leading foundation for Intel's multi–core server, desktop and mobile processors for computers later this year.
The first Intel Core microarchitecture products built on Intel's advanced 65nm process technology will deliver higher–performing, yet more energy–efficient processors that spur more stylish, quieter and smaller mobile and desktop computers and servers that can reduce electricity and real–estate associated costs, and provides critical capabilities such as enhanced security, virtualization and manageability for consumers and businesses.
Justin Rattner, Intel Senior Fellow and chief technology officer, explained that the Intel Core microarchitecture is the foundation for delivering greater energy–efficient performance first seen in the Intel Core Duo processor.
It builds on the power–saving philosophy begun with the Mobile Intel Pentium–M processor microarchitecture and greatly expands it, incorporating many new and leading–edge innovations as well as existing Intel Pentium 4 processor technologies such as wide data pathways and streaming instructions.
Intel expects processors based on the Intel Core microarchitecture, using Intel”s industry–leading 65nm manufacturing technology, to start shipping in the third quarter of 2006.
“The Intel Core microarchitecture is a milestone in enabling scalable performance and energy efficiency,” said Rattner. “Later this year it will fuel new dual–core processors and quad–core processors in 2007 that we expect to deliver industry leading performance and capabilities per watt. People will see systems that can be faster, smaller and quieter with longer battery life and lower electric bills.”
In his keynote, Rattner showed how the Conroe desktop processor could provide roughly a 40 percent boost in performance and a 40 percent decrease in power as compared to Intel”s current high–performing Intel Pentium D 950 processor. He also discussed significant gains in the Enterprise and Mobile areas as well.
Several advances mark the new microarchitecture:
-- Intel Wide Dynamic Execution –– Delivers more instructions per clock cycle, improving execution and energy efficiency. Every execution core is wider, allowing each core to complete up to four full instructions simultaneously using an efficient 14–stage pipeline.
-- Intel Intelligent Power Capability –– Includes features that further reduce power consumption by intelligently powering on individual logic subsystems only when required.
-- Intel Advanced Smart Cache –– This includes a shared L2 cache to reduce power by minimizing memory traffic and increase performance by allowing one core to utilize the entire cache when the other core is idle.
-- Intel Smart Memory Access –– Yet another feature that improves system performance by hiding memory latency and thus optimizing the use of data bandwidth out to the memory subsystem.
-- Intel Advanced Digital Media Boost –– Now all 128–bit SSE, SSE2 and SSE3 instructions execute within only one cycle. This effectively doubles the execution speed for these instructions which are used widely in multimedia and graphics applications.
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