IMEC shows optimizations for next-generation transistors

IMEC has achieved promising results in the race to scale CMOS to 22nm and below. The breakthroughs from its transistor scaling programs include a successful integration of the laser-anneal technique in a high-K/metal-gate ...

Novel technique shrinks size of nanotechnology circuitry

(PhysOrg.com) -- A University of Colorado at Boulder team has developed a new method of shrinking the size of circuitry used in nanotechnology devices like computer chips and solar cells by using two separate colors of light.

page 2 from 2