IBM Designed Power-based Chip for Microsoft Xbox 360

Together, IBM and Chartered's common platform offers Microsoft a unique dual-source capability that provides the highest level of manufacturing redundancy and flexibility.

The specialized chip, featuring customized and enhanced IBM intellectual property, was designed and developed by IBM and Microsoft to meet the unique requirements of the next generation Xbox 360 console.

"The Xbox 360 chip set was designed from the ground up specifically for high-definition gaming and entertainment," said Todd Holmdahl, corporate vice president, hardware for Xbox. "Working with IBM gave us the flexibility to design a processor to give game developers the kind of targeted power they need to make great games."

"Microsoft's aggressive timetable required that IBM take the Xbox 360 chip design from concept to full execution in just 24 months," said Ilan Spillinger, IBM Distinguished Engineer and director of the IBM Design Center for Xbox 360.

IBM engineers have been working with Microsoft to develop the chip since 2003 at IBM locations including Rochester, Minnesota; Austin, Texas; and Raleigh, North Carolina. Microsoft plans to formally launch Xbox 360 simultaneously in the United States, Japan and Europe later this year.

The chip features a customized version of IBM's industry leading 64-bit PowerPC core. The chip includes three of these cores, each with two simultaneous threads and clock speeds greater than 3 GHz. It features 165 million transistors and is fabricated using IBM's 90 nanometer Silicon on Insulator (SOI) technology to reduce heat and improve performance. The chip's innovative 21.6 GB/s Front Side Bus (FSB) Architecture was customized to meet the demanding throughput and latency requirements of the Xbox 360 gaming platform software.

Other Xbox 360 chip features include:

-- 3 identical multi-threaded PowerPC-based CPU cores operating at 3.2 GHz enhanced with specialized function VMX acceleration for gaming applications and a high speed 128-bit vector unit

-- 1 MByte Shared L2 Cache with custom logic for high-speed data streaming for graphics and system applications

-- 5.4 Gb/s per-pin Front Side Bus (with an aggregated bandwidth of 21.6 GBs)

-- Highly configurable and programmable utilizing eFUSE technology

Source: IBM