UMC's 90nm process does not meet the ITRS definition, according to Chipworks report

Chipworks Inc. the standard setting supplier of reverse engineering services, announced that they are analyzing the Xilinx XC3S200 Spartan-3 FPGA. Findings indicate a discrepancy in reported process techniques. Chipworks found that transistor gate lengths is less than 70nm, and a metal 1 (M1) pitch of ~250nm. While these do not meet the letter of the ITRS (International Technology Roadmap for Semiconductors) definition of 90nm feature sizes.

The device analyzed matches UMC's publicity and previous product investigated by Chipworks. It uses seven layers of copper, and one aluminum layer. Xilinx is using the 90nm technology to drive their target pricing down to under $12 for a one-million-gate FPGA and $2.95 for a 50,000 gate FPGA.

UMC's publicity for their 90nm L90 process details the M1 pitch as 240nm, and the gate length as 70nm, and shows the IMD as FSG at the upper metal layers, with low-k (k~2.7) at the lower levels.

Chipworks has seen that is claimed to be 90nm and is still using only the FSG (fluoro-silicate glass) that is universal in 130nm processes. Other 90nm technologies from Intel, Texas Instruments and Sony/Toshiba have all used low-k at the critical metal levels. Consequently, ChipWorks doubt is - can it be classified as a 90-nm part, or is it a shrunk 130nm device?

According to eeTimes , UMC executives fired back at a ChipWorks analysis of its 90-nm technology, saying the process can be offered in either a low-k and fluoro-silicate glass configuration. UMC also claims that its 90-nm transistors meet specifications in the International Technology Roadmap for Semiconductors (ITRS) roadmap.

"As far as the claim that our design rules do not meet the ITRS roadmap definition of 90-nm is concerned, it must be noted that although UMC offers a baseline technology for all of its process nodes, we also offer many different process options," UMC's spokewoman said.

More details at:
www.chipworks.com/