ASML Introduces the Industry's Highest NA Immersion Tool for Volume Chip Production at 45 nm Node

July 13, 2005

ASML Holding NV (ASML) today announced a new lithography system with the highest numerical aperture (NA) – 1.2 – in the semiconductor industry. The ASML TWINSCAN XT:1700i system is a 193 nm immersion scanner capable of volume chip production at the 45 nm node. The new system has a NA that jumped from 0.93 to 1.2, skipping the perceived, pre-immersion barrier of 1.0. The first shipment to a customer, a leading semiconductor manufacturer ordering its second ASML immersion system, will take place in Q1 2006.

The XT:1700i allows chip makers to improve resolution by 30 percent, the largest improvement in decades. Better resolution means more chips per wafer or more functionality per chip, thus increasing the value of each wafer. Additionally, the XT:1700i has the highest throughput currently available, 122 wafers per hour, for the 45 nm node.

“The XT:1700i is a milestone for the semiconductor industry. The continuation of Moore’s Law depended on either adapting existing or introducing new technology. ASML was able to enhance its fourth-generation immersion systems with a NA that is unchallenged in the market,” said Martin van den Brink, executive vice president, marketing and technology, ASML.

Additional customer benefits found in the XT:1700i include:

-- A new catadioptric lens design which combines refractive components with mirrors to create a hyper NA lens that is cost effective to manufacture and a consistent size with other ASML systems. Co-designed with ASML’s optics partner, Carl Zeiss SMT AG, the new lens will also extend to larger NAs in future products;

-- A maximum field size of 26 by 33 mm, the largest in the industry;

-- A polarized illumination system for improved contrast and exposure latitude at full throughput. With an NA of 1.2, polarization enhances resolution by 5 nm, from 50 to 45 nm;

-- A fourth-generation, dual-stage immersion tool. All previous generation tools are being used by real customers to produce real chips.

Explore further: IMEC demonstrates feasibility of double patterning immersion litho for 32nm node

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