3-D-compatible germanium nMOS gate stack with high mobility and superior reliability

December 23, 2016 by Hanne Degans, IMEC
3-D-compatible germanium nMOS gate stack with high mobility and superior reliability
Energy band diagrams of Si-passivated Ge nFET (b) without interface dipole and (c) with interface dipole at the high-k/SiO2 interface.

International Electron Devices Meeting 2016 (IEDM) - Dec. 7, 2016 - At this week's IEEE IEDM conference, imec, the world-leading research and innovation hub in nano-electronics and digital technologies showed for the first time a silicon (Si)-passivated germanium (Ge) nMOS gate stack with dramatically reduced interface defect density (DIT) reaching the same level as a Si gate stack and with high mobility and reduced positive bias temperature instability (PBTI). These promising results pave the way to Ge-based finFETs and gate all-around devices, as promising options for 5nm and beyond logic devices.

Today's results were achieved by band engineering using an interface dipole at high-k/SiO2 interface, and a H2 high-pressure anneal (HPA) finalizing the process flow. The interface dipole was formed on SiO2 layer by depositing a Lanthanum (La)SiO layer by (ALD), which is a 3D-compatible process. While a high DIT has been the leading concern for Si-passivated Ge nFET, it was dramatically reduced, for the first time, from 2x1012 cm-2eV-1 down to 5x1010 cm-2eV-1 around midgap using a combination of the LaSiO insertion and a H2 HPA. Consequently, electron mobility was increased (approximately 50 percent at peak) while PBTI reliability was improved thanks to the interface dipole-induced band engineering.

At IEEE IEDM, imec also presents a model for heterostructure resistivity (Rhi) analysis for highly doped semiconductors. Using this novel model, imec predicted that high-doping Si:P in a TiSix/Si:P/n-Ge contact stack helps to overcome the high contact resistance problem in Ge nMOS. With development of an advanced low-temperature Si:P epitaxy technique, imec demonstrated a TiSix/Si:P/n-Ge contact stack with record-low contact resistivity for n-Ge.

"Dedicated to push the boundaries of Moore's law, Ge-based devices are a key focus area or our research," stated An Steegen, Executive Vice President Semiconductor Technology and Systems. "These breakthrough achievements underscore our dedication to understanding the fundamental roadblocks that need to be overcome in order for Ge-based devices to become a viable solution for 5nm and beyond."

3-D-compatible germanium nMOS gate stack with high mobility and superior reliability
DIT profile of Si-passivated Ge gate stacks improved by LaSiO insertion and HPA.

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