Record-setting p-type transistor demonstrated: New design boasts the highest 'carry mobility' yet measured

January 2, 2013 by Larry Hardesty, Massachusetts Institute of Technology
Record-setting p-type transistor demonstrated: New design boasts the highest 'carry mobility' yet measured
In this micrograph of an experimental transistor, blue highlighting indicates areas of "strain," where germanium atoms have been forced closer together than they find comfortable. One of the reasons for the transistor's record-setting performance is that the strain has been relaxed in the lateral direction. Image: Winston Chern and James Teherani

Almost all computer chips use two types of transistors: one called p-type, for positive, and one called n-type, for negative. Improving the performance of the chip as a whole requires parallel improvements in both types.

At the IEEE's International Electron Devices Meeting (IEDM) in December, researchers from MIT's Laboratories (MTL) presented a p-type transistor with the highest "" yet measured. By that standard, the device is twice as fast as previous experimental p-type and almost four times as fast as the best commercial p-type transistors.

Like other experimental high-performance transistors, the new device derives its speed from its use of a material other than silicon: in this case, germanium. Alloys of germanium are already found in commercial chips, so germanium transistors could be easier to integrate into existing chip- than transistors made from more .

The new transistor also features what's called a trigate design, which could solve some of the problems that plague at extremely small sizes (and which Intel has already introduced in its most advanced chip lines). For all these reasons, the new device offers a tantalizing path forward for the microchip industry—one that could help sustain the rapid increases in , known as Moore's Law, that consumers have come to expect.

Pluses and minuses

A transistor is basically a switch: In one position, it allows charged particles to flow through it; in the other position, it doesn't. In an n-type transistor, the particles—or —are , and their flow produces an ordinary .

In a p-type transistor, on the other hand, the charge carriers are positively charged "holes." A p-type semiconductor doesn't have enough electrons to balance out the positive charges of its atoms; as electrons hop back and forth between atoms, trying futilely to keep them electrically balanced, holes flow through the semiconductor, in much the way waves propagate across water molecules that locally move back and forth by very small distances.

"Carrier mobility" measures how quickly charge carriers—whether positive or negative—move in the presence of an electric field. Increased mobility can translate into either faster transistor switching speeds, at a fixed voltage, or lower voltage for the same switching speed.

For decades, each logic element in a computer chip has consisted of complementary n-type and p-type transistors whose clever arrangement drastically reduces the chip's power consumption. In general, it's easier to improve carrier mobility in n-type transistors; the MTL researchers' new device demonstrates that p-type transistors should be able to keep up.

Handling the strain

Judy Hoyt, a professor of electrical engineering and computer science; her graduate students Winston Chern, lead author on the new paper, and James T. Teherani; Pouya Hashemi, who was an MIT postdoc at the time and is now with IBM; Dimitri Antoniadis, the Ray and Maria Stata Professor of Electrical Engineering; and colleagues at MIT and the University of British Columbia achieved their record-setting hole mobility by "straining" the germanium in their transistor—forcing its atoms closer together than they'd ordinarily find comfortable. To do that, they grew the germanium on top of several different layers of silicon and a silicon-germanium composite. The germanium atoms naturally try to line up with the atoms of the layers beneath them, which compresses them together.

"It's kind of a unique set of material structures that we had to do, and that was actually fabricated here, in the MTL," Hoyt says. "That's what enables us to explore these materials at the limits. You can't buy them at this point."

"These high-strain layers want to break," Teherani adds. "We're particularly successful at growing these high-strain layers and keeping them strained without defects." Indeed, Hoyt is one of the pioneers of strained-silicon transistors, a technology found today in almost all commercial . At last year's IEDM, she and Eugene Fitzgerald, the Flemings-SMA Professor of Materials Science and Engineering at MIT, received the IEEE's Andrew S. Grove Award for outstanding contributions to solid-state devices and technology. The award announcement cited Hoyt's "groundbreaking contributions involving strained-silicon semiconductor materials."


Another crucial aspect of the new transistor is its trigate design. If a transistor is a switch, throwing the switch means applying a charge to the transistor's "gate." In a conventional transistor, the gate sits on top of the "channel," through which the charge carriers flow. As transistors have grown smaller, their gates have shrunk, too. But at smaller sizes, that type of lockstep miniaturization won't work: Gates will become too small to reliably switch transistors off.

In the trigate design, the channels rise above the surface of the chip, like boxcars sitting in a train yard. To increase its surface area, the gate is wrapped around the channel's three exposed sides—hence the term "trigate." By demonstrating that they can achieve high hole mobility in trigate transistors, Hoyt and her team have also shown that their approach will remain useful in the chips of the future.

Explore further: Nanowires made of 'strained silicon' show how to keep increases in computer power coming

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2.3 / 5 (4) Jan 02, 2013
"Almost all computer chips use two types of transistors: one called p-type, for positive, and one called n-type, for negative."

This seems quite an inaccurate headline. Or at least misleading.

Actually this article generally seems to have a really poor way of explaining transistors. Also leaving out of a lot of pertinent detail. Or is it just me?
4.5 / 5 (4) Jan 02, 2013
@neutrino64: The article is referring to CMOS transistors, in which a p-channel MOS transistor is paired with an n-channel MOS transistor. This is done so that essentially no power is drawn except when switching.

The article does give a brief summary about how a transistor works, but the part about the gate controlling the 'switch' was put with the tri-gate discussion rather than with the discussion on the switch controlling the current flow.

The article is short on details, but then it is a summary of a conference paper and not the paper itself. This fits with being a summary of science news, rather than diving into the details of any one area.
1 / 5 (2) Jan 02, 2013
*please someone removes this*
2.5 / 5 (2) Jan 02, 2013

Fair enough. I guess in my opinion it's better to either get into a bit more accuracy and details or give more of an over-view explanation.

This article just seemed to try to shoot somewhere in the middle, not addressing the needs of either the general public or people with personal interest in the subject. But I understand it's a difficult line to walk. Either way, interesting stuff.
4 / 5 (1) Jan 02, 2013
Fair enough. I guess in my opinion it's better to either get into a bit more accuracy and details or give more of an over-view explanation.

I think physorg tries to keep its articles within a certain word range generally, which allows it to be good for a quick reading, and keeps it from becoming an interminable dissertation.

It's only meant to scratch the surface - and while often it feels too rushed, I can always go to wikipedia or another relevant site if I am left confused or wish to go more in depth.
5 / 5 (1) Jan 02, 2013
Fair point. Anyway, don't want to derail the conversation from the topic. Appreciate the feedback.
2.5 / 5 (2) Jan 03, 2013
I think physorg tries to keep its articles within a certain word range generally, which allows it to be good for a quick reading, and keeps it from becoming an interminable dissertation.
It just reprints the university news. You're barking at the wrong tree - you should write a letter to MIT Media Relations staff, who is responsible for superficial reporting about MIT research.
1 / 5 (1) Jan 03, 2013
IMO this article is rather good, it just lack some illustrations, which makes it less comprehensible - like the trigate design, the more illustrative explanation of the mechanism of stress to charge carrier mobility and so on. The principle is the same like with electrons inside of peeled-off graphene layer: due the mutual stress the electrons are squeezed each other, their repulsive forces overlap and compensate mutually, so that the charge carriers are moving freely in ballistic mechanism, i.e. in similar way like the electrons within superconductors.
not rated yet Jan 03, 2013
Interesting work! I wonder if the strain can be maintained at small processor geometries?

As the tri-gate gets smaller, the number of atoms that make up the length and width becomes smaller. At, say, 25 nm width this number would be app. 75 atoms. One can immagine that the strain varies with such a small number of participating atoms, making the strain large in some devices (high hole mobility) and smaller in others (lower hole mobility). Or is this not correct? At least with doping, the small number of atoms have been shown to increase the transistor-to-transistor variation.
2.3 / 5 (3) Jan 03, 2013
The level of strain is rather limited with signal/noise ratio - as Esaki has found at the beginning of 60's the electrons within highly strained semiconductor structures tend to oscillate in high frequency noise. The strain increases the free path for carrier motion and at the moment, when it exceeds the PN structure size, nothing can keep the electrons there in defined state. Therefore the processing speed is always balanced with density of integration achievable. Currently is easier to achieve higher processing speed with higher integration density and parallelization of CPU cores, which is the reason why the CPU frequency stagnates during last ten years.
1 / 5 (1) Jan 03, 2013
@valeria - It's not that your comment is incorrect, but I believe that you are getting rated so low because your comment is convoluted and unnecessarily complicated, as if you are trying to make yourself out to be smarter than everyone else.

Let me summarize the challenges in a simpler, more straightforward way.

Currently, increasing clock speed in chips creates too much signal noise that the silicon transistor cannot adequately manage beyond a certain point. When the noise becomes too high, of course the transistors do not switch as reliably (Creating errors), and create excess heat that only compounds compounds the problem.

I assume that the commenters on this site are wise enough to realize that multiple cores are a workaround, if the software can be parallelized, but are somewhat limited in how much utility and scalability they can provide for general consumer computing other than graphics applications.
3 / 5 (2) Jan 04, 2013
..are getting rated so low because your comment is convoluted and unnecessarily complicated
I'm downvoted usually with lite account only, who is 1) dedicated voting troll and w2) who labels the posts mindlessly at personal, not factual basis. I just don't like logical steps in reasoning. So if you write "increasing clock speed in chips creates too much signal noise", 1) you're getting out of carrier mobility context of this article 2) you don't explain the actual nature of problem.

Of course the increasing of clocking speed increases noise/signal ratio - but this is just the problem, which the faster transistors should solve - or not? But just the slightly deeper analysis (which is probably too complex for superficial readers of PO though) demonstrates, this problem is principal and it cannot be removed with using of transistors with higher carrier mobility, because the technology already hit the Heisenberg's uncertainty principle.
1 / 5 (2) Jan 04, 2013
The Heisenberg's uncertainty principle says, if we increase the speed of electrons, we'll decrease their localization accordingly - which just prohibits the further miniaturization of transistors. This is somewhat deeper problem than that "increasing clock speed in chips", which "creates too much signal noise" - don't you think?

I've no need to pretend to be smarter than than everyone else - I'm just focused to the actual problem. Which is something, which is difficult to expect from contemporary generation of mainstream physicists, who are required not only to solve problems, but to provide continuation of the job when this problem is getting solved.

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