Smallest logic circuit fabricated with single-electron transistors

November 21, 2012 by Lisa Zyga, feature

Researchers have fabricated a half-adder logic circuit with just three SETs and two FETs, compared with 20 FETs in a traditional CMOS half-adder. The new half-adder’s small size and ultra-low power consumption make it promising for next-generation terabit-level nanoelectronics. Image credit: S. J. Kim, et al. ©2012 American Institute of Physics
(—In order to meet the growing demand for small-scale, low-power computing, researchers have been aggressively downscaling silicon-based computing components. These components include transistors and logic circuits, both of which are used to process data in electronic devices by controlling voltage. However, the smallest type of logic circuit, called a half-adder, has not yet been fabricated on as small a scale as it could be.

In a new study, a team of researchers from South Korea, Japan, and the UK has fabricated a half-adder logic circuit using just five transistors Their paper, titled "One electron-based smallest flexible logic cell," is published in a recent issue of Applied Physics Letters.

"We made the first successful implementation of a one-electron-based half-adder (HA) that is the smallest arithmetic block for the single-electron transistor (SET) multi-valued (MV) logic family," Jung-Bum Choi, Professor of Physics and the Director of the Physics Department & Research Institute for Nano Science and Technology at Chungbuk National University in Cheongju, South Korea, told "All logic circuits are just combinations of numerous HAs. The one-electron HA operates at nA-levels with low-power consumption. Moreover, the HA has two additional functionalities: multi-valued and flexible. Therefore, the one-electron HA cell will provide a basis for ultra-high density and low-power ultra-large-scale integration, which is one of the most critical problems facing future small mobile IT systems."

As the smallest arithmetic block of , a half-adder adds two single-digit numbers and generates two outputs: sum and carry, where the carry is added to the next digit in multi-digit addition. In a traditional CMOS half-adder, at least 20 field-effect (FETs) are needed for a half-adder. Here, the scientists fabricated a half-adder with just three SETs and two FETs.

In addition, the scientists showed that the half-adder mode could be switched to a subtraction mode simply by changing the control gate on an SET. In subtraction mode, the sum and carry functions became difference and borrow functions.

"The one-electron HA adapts a new SET structure with two symmetrical side-gates, which enables us to use only three SETs and two FETs components," Choi said. "This cell structure has a considerable advantage in the number of components compared with the traditional CMOS counterpart, where at least 20 FETs are needed for an HA. Moreover, the CMOS is binary, that is, operates with 0 or 1. In contrast, the one-electron HA is multi-valued and flexible, resulting in effective integration density. However, the one-electron HA has previously been delayed in its implementation because the three SETs should have identical phases in their Coulomb oscillations, which has been a very difficult problem occurring mainly due to a highly complicated nanofabrication process."

Due to its small size, ultra-low power consumption, and fast operation, the half-adder logic cell could prove useful for next-generation terabit-level nanoelectronics. Choi hopes it will have applications in the memory and CPU in both mobile systems and PCs. Although it currently operates at a low temperature of 10K, the researchers are currently working on ways to implement the logic circuit at room temperature.

"The flexible multi-valued one-electron HA cell, even though it operates at a low temperature of 10K, provides the smallest block for the SET MV logic family," Choi said. "Most recently, we successfully fabricated the room-temperature multiple switching Si-SET. Using these SETs as basic elements, we expect the possible implementation of the single-electron flexible MV half-adder operating at room-temperature, which is now being undertaken."

Explore further: Toward achieving one million times increase in computing efficiency

More information: S. J. Kim, et al. "One electron-based smallest flexible logic cell." Applied Physics Letters 101, 183101 (2012). DOI: 10.1063/1.4761935

Journal reference: Applied Physics Letters search and more info website


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not rated yet Nov 22, 2012
10 K operation is not bad for a SET, that is, if it has resonable performance in other characteristics. I would also commend the writer for making sure that there is a scale bar in the SEM image. Well done!
1 / 5 (1) Nov 22, 2012
One wonders if the cost of cooling a system to these temperatures is even worth the returns compared to higher operating temperatures or less efficient circuitry?

This is ridiculously, stupidly impractical, even for military, university, or corporate super-computers.
4 / 5 (1) Nov 25, 2012
@Lurker: Yes, 10K would be impractical, but that is just a stepping stone. Please re-read their concluding remark:
"Most recently, we successfully fabricated the room-temperature multiple switching Si-SET. Using these SETs as basic elements, we expect the possible implementation of the single-electron flexible MV half-adder operating at room-temperature, which is now being undertaken."

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