News tagged with chip packages
3M and IBM to develop new types of adhesives to create 3D semiconductors
3M and IBM announced that the two companies plan to jointly develop the first adhesives that can be used to package semiconductors into densely stacked silicon “towers.” The companies are aiming ...
Sep 08, 2011 |
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Elpida begins sample shipments of DDR3 SDRAM (x32) based on TSV stacking technology
Elpida Memory today announced that it has begun sample shipments of the industry's first DDR3 SDRAM (x32-bit I/O configuration) made using TSV (Through Silicon Via) stacking technology. The sample is a low-power 8-gigabit ...
Jun 28, 2011 |
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Elpida achieves 4-Layer 0.8mm mobile RAM package
Elpida Memory today announced that its researchers have developed the technology to mass manufacture a 0.8mm four-layer DRAM package, the thinnest memory device in the DRAM industry.
Jun 22, 2011 |
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Researchers develop unique combination of elements for thermal nanotape
Semiconductor Research Corporation (SRC) and researchers from Stanford University have developed a novel combination of elements that yields a unique nanostructure material for packaging. This advance should allow longer ...
Nanotechnology / Nanomaterials
Jan 24, 2011 |
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New materials for electronic packaging: Researchers improve energy costs in chip-making
Carnegie Mellon University and Intel Corporation will unveil a new class of materials called solder magnetic nanocomposites that could help streamline the process of computer electronic packaging. The milestone research will ...
Nanotechnology / Nanomaterials
Jan 19, 2010 |
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Samsung Develops Advanced Packaging Technology to Achieve a 0.6mm-thick 8-chip Package
Samsung Electronics announced today that it has developed the world's thinnest multi-die package, one that measures a mere 0.6mm in height. Designed initially for 32 gigabyte (GB) densities, the new memory ...
Nov 05, 2009 |
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Elpida Completes Development of Cu-TSV (Through Silicon Via) Multi-Layer 8-Gigabit DRAM
Elpida Memory today announced that it has completed development of a Cu-TSV (Through Silicon Via) multi-layer 8-Gigabit DRAM.
Aug 31, 2009 |
4 / 5 (5) |
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NEC Develops a Three-Dimensional Chip-Stacked Flexible Memory
NEC Corporation announced today the development of chip-stacked flexible memory, which can be used to achieve a new system-on-chip (SoC) architecture. The new SoC's architecture consists of separate logic ...
Feb 10, 2009 |
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