Elpida develops industry's smallest 30nm process 2-Gigabit DDR3 SDRAM

Sep 29, 2010

Elpida Memory, Inc., Japan's global supplier of Dynamic Random Access Memory (DRAM), today announced that it had completed development of a 30nm process 2-gigabit DDR3 SDRAM.

The new 2-gigabit DDR3 SDRAM used 30nm-level advanced process migration technology to create the DRAM industry's smallest-level 2-gigabit DDR3 SDRAM. It achieves 45% more chips per wafer compared with Elpida's 40nm process products. Also, the new process design developed by Elpida will help contain rising chip costs associated with process migration. As a result, the 2-gigabit DDR3 is slated to become an extremely cost-competitive product.

Elpida's new chip meets the JEDEC specs for the high-speed DDR3-1866 and 1.35V low-voltage, high-speed DDR3L-1600 , both expected to become mainstream industry products in 2011. Also, the 30nm DDR3 SDRAM is eco-friendly. As a DDR3 SDRAM it achieves one of the industry's lowest levels of electric current usage (approximately 15% less operating and approximately 10% less standby usage compared with Elpida's 40nm products), which contributes to lower PC and digital consumer electronics .

Elpida plans to begin sample shipments of the newly developed DDR3 SDRAM in December 2010. Volume production is expected to commence in the same month.

Elpida will apply the new 30nm process technology to its Mobile RAM products. The company also plans to use the process together with Through Silicon Via (TSV) technology to support one-chip memory solutions for mobile phones, digital still cameras and PC DRAMs.

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Quantum_Conundrum
5 / 5 (2) Sep 29, 2010
What gives?

Based on simple geometry, they should have been able to fit about 77.77% more chips per wafer...

Is the 32.72% discrepancy represented entirely by circuitry for buses and power supply of the chips?

It would seem that the transistors are miniaturizing faster than the wiring, and that moreover, the law of large numbers is at play because the wires and other "logic" and power is taking up a higher and higher percentage of the chip's area and volume as compared to individual transistors.
plasma_guy
5 / 5 (1) Oct 10, 2010
What gives?

Based on simple geometry, they should have been able to fit about 77.77% more chips per wafer...

Is the 32.72% discrepancy represented entirely by circuitry for buses and power supply of the chips?

It would seem that the transistors are miniaturizing faster than the wiring, and that moreover, the law of large numbers is at play because the wires and other "logic" and power is taking up a higher and higher percentage of the chip's area and volume as compared to individual transistors.


I think that is a good point and also the scaling may not be exactly 40 nm to 30 nm but 40-something to 30-something. It is interesting they can do something this aggressive. Maybe they are trying to match Samsung's pace.

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