Epson Develops Graphics Engine-Equipped Application Processor for Effortlessly Rendering Screens

Jan 28, 2010
Epson Develops Graphics Engine-Equipped Application Processor for Effortlessly Rendering Screens

Seiko Epson Corporation today announced it has developed and begun shipping samples of the S1C33L26, an application processor ideal for product applications requiring high-resolution liquid crystal displays (LCDs), such as control panels for office and factory automation equipment, and high-performance remote controls.

Samples of the new processor in a TQFP24-144 package are priced at ¥2,000 (~$22.2) per unit. Volume production is scheduled to commence in May of this year with a monthly output of 100,000 units. The will be available as a bare chip and in TQFP, QFP and BGA packages.

The S1C33L26 comes equipped with a graphic draw engine (GE) that provides hardware support for functions required to render richly varied displays, including points, lines, triangles, squares, circles, re-sizing and rotation, all operated via simple commands. The S1C33L26 can draw lossless compression image data, which reduces both CPU load and the size of image data ROM.

The inclusion of an LCD and 4-level grayscale QVGA-equivalent VRAM in a single-chip solution means the S1C33L26 supports high resolutions, such as VGA 16M color, when expanded with external VRAM. The S1C33L26 also supports a DMA-capable LCD driver interface thanks to the data transfer efficiency of its LCD module, whose LCD driver contains built-in VRAM. Moreover, the S1C33L26 can further reduce CPU load by utilizing its 32-bit multiplier and 16-bit divider as DSP for audio data playback, such as ADPCM. An I2S interface also makes DAC for audio and other external connections a simple matter.

This product is equipped with a 32-bit RISC CPU core, a graphics engine (GE), a generic DMA controller, a USB-FS device controller, an LCD controller, a PWM control timer/counter, various interfaces (SIO, SPI, UART, I2C, I2S), ADC, RAM, shared VRAM, RTC with separate power supply, a NAND flash interface, and other components.


Explore further: Technology to reduce network switches in cluster supercomputers by 40 percent

More information: global.epson.com/newsroom/2010/pdf/100128_spec.pdf

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