First 3-D processor runs at 1.4 Ghz on new architecture

Sep 15, 2008

(PhysOrg.com) -- The next major advance in computer processors will likely be the move from today's two-dimensional chips to three-dimensional circuits, and the first three-dimensional synchronization circuitry is now running at 1.4 gigahertz at the University of Rochester.

Unlike past attempts at 3-D chips, the Rochester chip is not simply a number of regular processors stacked on top of one another. It was designed and built specifically to optimize all key processing functions vertically, through multiple layers of processors, the same way ordinary chips optimize functions horizontally. The design means tasks such as synchronicity, power distribution, and long-distance signaling are all fully functioning in three dimensions for the first time.

"I call it a cube now, because it's not just a chip anymore," says Eby Friedman, Distinguished Professor of Electrical and Computer Engineering at Rochester and faculty director of the pro of the processor. "This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2D chip."

Friedman, working with engineering student Vasilis Pavlidis, says that many in the integrated circuit industry are talking about the limits of miniaturization, a point at which it will be impossible to pack more chips next to each other and thus limit the capabilities of future processors'. He says a number of integrated circuit designers anticipate someday expanding into the third dimension, stacking transistors on top of each other.

But with vertical expansion will come a host of difficulties, and Friedman says the key is to design a 3-D chip where all the layers interact like a single system. Friedman says getting all three levels of the 3-D chip to act in harmony is like trying to devise a traffic control system for the entire United States—and then layering two more United States above the first and somehow getting every bit of traffic from any point on any level to its destination on any other level—while simultaneously coordinating the traffic of millions of other drivers.

Complicate that by changing the two United States layers to something like China and India where the driving laws and roads are quite different, and the complexity and challenge of designing a single control system to work in any chip begins to become apparent, says Friedman.

Since each layer could be a different processor with a different function, such as converting MP3 files to audio or detecting light for a digital camera, Friedman says that the 3-D chip is essentially an entire circuit board folded up into a tiny package. He says the chips inside something like an iPod could be compacted to a tenth their current size with ten times the speed.

What makes it all possible is the architecture Friedman and his students designed, which uses many of the tricks of regular processors, but also accounts for different impedances that might occur from chip to chip, different operating speeds, and different power requirements. The fabrication of the chip is unique as well. Manufactured at MIT, the chip must have millions of holes drilled into the insulation that separates the layers in order to allow for the myriad vertical connections between transistors in different layers.

"Are we going to hit a point where we can't scale integrated circuits any smaller? Horizontally, yes," says Friedman. "But we're going to start scaling vertically, and that will never end. At least not in my lifetime. Talk to my grandchildren about that."

Provided by University of Rochester

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User comments : 9

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ZeroDelta
4.8 / 5 (4) Sep 15, 2008
And they are going to deal with excess heat how?
cougar1701
4.6 / 5 (5) Sep 15, 2008
micro channel water cooling
TopherT
4.5 / 5 (2) Sep 15, 2008
Computronium here we come.
mattytheory
4 / 5 (1) Sep 15, 2008
been waiting for this for a LONG time. good to see they are finally making progress in this field. i also like how they are considering re-developing the architecture for each CPU "layer".
dirk_bruere
2 / 5 (2) Sep 15, 2008
Just stacking chips on top of each other might be good for a factor of 10x or so, but not much more.
Harkonnen
1 / 5 (3) Sep 15, 2008
Hence forth, from now on all 3-D processors shall be known as CHUBEs!!!!

:-P
weewilly
3 / 5 (4) Sep 15, 2008
Has anyone given any thought to how to improve the user of these finely improved CPU's.? I'll sign up.
jburchel
1 / 5 (1) Sep 16, 2008
Just stacking chips on top of each other might be good for a factor of 10x or so, but not much more.


Not so, and no evidence cited to support the erroneous conclusion. Efficiency improvement is combinatorial not linear with stacking implemented to its optimum, which will of course not be its first generation, but to say 10x is the maximum gain is just stupid. Eventually thousands of layers may truly lead to "cube shape", not just slightly thicker square, and millions of interconnection points on each horizontal surface. Losers have been whining that Moore's Law is at its end since 1970, and they get proven wrong every time, but still they keep on whining the same old crap. Eventually I guess they will happen to be right, just like a broken clock, but so far, I don't see evidence we are in trouble anytime before 2020. So please just shut up naysayers and let the innovators do their work, and be happy with the extra taxes you get from their superior productivity...
poi
4 / 5 (1) Sep 17, 2008
Remember "Contact" (1997)
wiki: "Specialists are brought in to attempt to decode the drawings but have no luck. As Arroway returns home one night, she is contacted by Hadden, offering to meet her at a remote airport. Aboard his private plane, Hadden introduces himself to Arroway, and the reveals that he has found the means to decode the message, as the pages are meant to be interpreted in three dimensions."
-efficiency is in 3d; we're starting to think like the aliens!