IBM Alliances Announce Advancement in High-K/Metal Gate Technology

Dec 14, 2007
32nm SRAM with High-K/Metal Gate
The world´s smallest SRAM cell using High-K/Metal Gate (<0.15um2). Credit: IBM

IBM and its joint development partners -- AMD, Chartered Semiconductor Manufacturing, Freescale, Infineon, and Samsung -- announced an innovative approach to speed the implementation of a breakthrough material known as "high-k/metal gate" in next generation 32 nanometer (32nm) computer chips.

This new approach, an industry first based on what engineers call a “high-k gate-first” process, is designed to provide a simpler, less time consuming way for clients to migrate to high-k metal gate technology in order to secure benefits that include improved performance and reduced power consumption.

Chips using the new technique will support a range of applications - from low power computer microchips targeted at wireless and other consumer-oriented devices to high performance microprocessors for games and enterprise computing. This new approach to implementing high-k/metal gate will be available to IBM alliance members and their clients in the second half of 2009.

Video: 32 nanometer high-k metal gate chips

On January 29, 2007, IBM and its research partners (including Sony and Toshiba) introduced the "high-k/metal gate” innovation as the basis for a long-sought improvement to the transistor – the tiny on/off switch that serves as the basic building block of virtually all microchips made today. Using the high-k/metal gate material in a critical portion of the transistor that controls its primary on/off switching function enabled the development of 32nm chip circuitry that is designed to be smaller, faster, and more power-efficient than previously thought possible.

Using high-k/metal gate IBM and its Alliance Partners have been able to successfully shrink the size of a chip by up to 50 percent as compared to the previous technology generation while improving a number of other performance specifications. For example, high-k metal gate chips save about 45 percent total power, an increasingly critical metric in all electronics applications.

Together these improvements will help to increase functionality and performance with lower power consumption and improved battery life in mobile devices. For microprocessor applications, this innovation also enables up to 30 percent higher performance as documented in measurements performed by IBM and its Alliance Partners at IBM’s East Fishkill, NY semiconductor manufacturing facility.

"IBM’s alliances have demonstrated the ‘high-k gate-first’ approach in a manufacturing environment, an achievement that provides clients with a simple, scalable pathway to incorporating the high k material innovation in semiconductor development without introducing additional design complexity," said Gary Patton, vice president, IBM's Semiconductor Research and Development Center on behalf of IBM's technology alliances. "This industry leading development comes from leveraging the collective engineering talent and breadth of market experience across the six Alliance Partner companies, as well as world class R&D facilities such as UAlbany NanoCollege’s Albany NanoTech complex, in order to maintain an aggressive road map.”

IBM and its Alliance Partners have developed low-power foundry Complementary Metal Oxide Semiconductor (CMOS) technology using the 'high-k gate-first' approach and have demonstrated the first 32nm ultra dense static random access memory (SRAM) in this low power technology with cell sizes below 0.15um2.

SRAMs are a key building block of computer chip designs and an excellent indicator of the readiness of a technology. The unique characteristics of the high-k material reduces total chip power consumption by as much as a 45 percent compared to the previous generation, a critical technology factor for achieving longer battery life in hand held devices such as cell phones, pagers, and PDAs.

In addition, IBM and its Alliance Partners have incorporated the high-k innovation into a new generation of high performance Silicon-On-Insulator (SOI) technology at 32nm. The unique high-k material properties enable a transistor speed improvement of greater than 30 percent over the previous generation of high performance Silicon-On-Insulator (SOI) technology.

The SRAM demonstrated in this new generation of high performance technology functions at a lower voltage - an improvement that reduces the energy consumption for microprocessor applications. The use of SOI provides a significant performance and power benefit, which, in combination with the high-k/metal gate advancement, will help the technology deliver energy efficient chips used in applications such as games, personal computers, and high end computing systems.

Source: IBM

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