Rice's silicon oxide memories catch manufacturers' eye

Jul 10, 2014
This scanning electron microscope image and schematic show the design and composition of new RRAM memory devices based on porous silicon oxide that were created at Rice University. Credit: Tour Group/Rice University

(Phys.org) —Rice University's breakthrough silicon oxide technology for high-density, next-generation computer memory is one step closer to mass production, thanks to a refinement that will allow manufacturers to fabricate devices at room temperature with conventional production methods.

First discovered five years ago, Rice's memories are a type of two-terminal, "resistive random-access memory" (RRAM) technology. In a new paper available online in the American Chemical Society journal Nano Letters, a Rice team led by chemist James Tour compared its RRAM technology to more than a dozen competing versions.

"This memory is superior to all other two-terminal unipolar resistive memories by almost every metric," Tour said. "And because our devices use silicon oxide—the most studied material on Earth—the underlying physics are both well-understood and easy to implement in existing fabrication facilities." Tour is Rice's T.T. and W.F. Chao Chair in Chemistry and professor of mechanical engineering and nanoengineering and of computer science.

Tour and colleagues began work on their breakthrough RRAM technology more than five years ago. The basic concept behind resistive memory devices is the insertion of a dielectric material—one that won't normally conduct electricity—between two wires. When a sufficiently high voltage is applied across the wires, a narrow conduction path can be formed through the dielectric material.

The presence or absence of these conduction pathways can be used to represent the binary 1s and 0s of digital data. Research with a number of dielectric materials over the past decade has shown that such conduction pathways can be formed, broken and reformed thousands of times, which means RRAM can be used as the basis of rewritable random-access memory.

RRAM is under development worldwide and expected to supplant flash memory technology in the marketplace within a few years because it is faster than flash and can pack far more information into less space. For example, manufacturers have announced plans for RRAM prototype chips that will be capable of storing about one terabyte of data on a device the size of a postage stamp—more than 50 times the data density of current .

This illustration depicts the rewriteable crystalline filament pathway in Rice University's porous silicon oxide RRAM memory devices. Credit: Tour Group/Rice University

The key ingredient of Rice's RRAM is its dielectric component, silicon oxide. Silicon is the most abundant element on Earth and the basic ingredient in conventional microchips. Microelectronics fabrication technologies based on silicon are widespread and easily understood, but until the 2010 discovery of conductive filament pathways in silicon oxide in Tour's lab, the material wasn't considered an option for RRAM.

Since then, Tour's team has raced to further develop its RRAM and even used it for exotic new devices like transparent flexible memory chips. At the same time, the researchers also conducted countless tests to compare the performance of silicon oxide memories with competing dielectric RRAM technologies.

"Our technology is the only one that satisfies every market requirement, both from a production and a performance standpoint, for nonvolatile memory," Tour said. "It can be manufactured at room temperature, has an extremely low forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, exceptional switching speeds and excellent cycling endurance."

In the latest study, a team headed by lead author and Rice postdoctoral researcher Gunuk Wang showed that using a porous version of silicon oxide could dramatically improve Rice's RRAM in several ways. First, the porous material reduced the forming voltage—the power needed to form conduction pathways—to less than two volts, a 13-fold improvement over the team's previous best and a number that stacks up against competing RRAM technologies. In addition, the porous silicon oxide also allowed Tour's team to eliminate the need for a "device edge structure."

"That means we can take a sheet of porous silicon oxide and just drop down electrodes without having to fabricate edges," Tour said. "When we made our initial announcement about silicon oxide in 2010, one of the first questions I got from industry was whether we could do this without fabricating edges. At the time we could not, but the change to porous silicon oxide finally allows us to do that."

This electron microscope image shows the surface of the nanoporous silicon-oxide material used in Rice University's new RRAM memory devices. The red areas highlight gaps, or voids, in the material's amorphous silicon-oxide coating. Credit: Tour Group/Rice University

Wang said, "We also demonstrated that the porous silicon oxide material increased the endurance cycles more than 100 times as compared with previous nonporous silicon oxide memories. Finally, the porous silicon oxide material has a capacity of up to nine bits per cell that is highest number among oxide-based memories, and the multiple capacity is unaffected by high temperatures."

Tour said the latest developments with oxide—reduced forming voltage, elimination of need for edge fabrication, excellent endurance cycling and multi-bit capacity—are extremely appealing to memory companies.

"This is a major accomplishment, and we've already been approached by companies interested in licensing this new technology," he said.

Study co-authors—all from Rice—include postdoctoral researcher Yang Yang; research scientist Jae-Hwang Lee; graduate students Vera Abramova, Huilong Fei and Gedeng Ruan; and Edwin Thomas, the William and Stephanie Sick Dean of Rice's George R. Brown School of Engineering, professor in mechanical engineering and materials science and in chemical and biomolecular engineering.

Explore further: Innovative electrodes allow new computer memory technologies to be compatible with existing circuitry

More information: Nano Letters, pubs.acs.org/doi/abs/10.1021/nl501803s

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verkle
2 / 5 (2) Jul 10, 2014
This is really cool. I would like to see more information on which manufacturers are going to use Rice's technology.

Is Au required for fabrication? If so, it is going to be a very expensive production compared to standard silicon with Cu or Al.

DonGateley
2 / 5 (1) Jul 10, 2014
Nine bits per cell? Can anyone explain what they mean by that? 512 controllable and discernable levels of resistance?
RealScience
5 / 5 (2) Jul 10, 2014

Is Au required for fabrication? If so, it is going to be a very expensive production compared to standard silicon with Cu or Al.

It is surprising how little gold or platinum would actually be needed. In the picture it looks like two layers of perhaps 0.2 microns each, so if a 'postage stamp' is 20 mm x 30 mm, that's on the order of 1/4 of a cubic millimeter of gold or platinum per device. That is only about 5 milligrams, or 1/7000 of a Troy ounce, or very roughly 25 cents worth of precious metals. If they can truly deliver a terabyte in a postage-stamp-sized device, the precious metals cost is very roughly 25 cents per terabyte.

Nine bits per cell? Can anyone explain what they mean by that? 512 controllable and discernable levels of resistance?

Yes, that's what it sounds like, and some experimental phase-change memories have hit over a hundred discernible levels so 512 levels is impressive but not unreasonable.
DonGateley
5 / 5 (1) Jul 10, 2014
@RealScience: an intrinsic ECC bit could be really useful.
verkle
5 / 5 (1) Jul 11, 2014
It is surprising how little gold or platinum would actually be needed. In the picture it looks like two layers of perhaps 0.2 microns each, so if a 'postage stamp' is 20 mm x 30 mm, that's on the order of 1/4 of a cubic millimeter of gold or platinum per device. That is only about 5 milligrams, or 1/7000 of a Troy ounce, or very roughly 25 cents worth of precious metals. If they can truly deliver a terabyte in a postage-stamp-sized device, the precious metals cost is very roughly 25 cents per terabyte.


Even at this scale, for chip fabrication an additional 25 cents per device is huge. This is a ton of gold. This is why many chip vendors have moved away from even occasional Au bonding.

RealScience
5 / 5 (1) Jul 11, 2014
@RealScience: an intrinsic ECC bit could be really useful.

Yes, an extra bit per cell suggests a built-in ECC, but with multiple bits in the same cell one has to be careful.
Nine bits looks looks like a byte with a parity bit, but the nine bits share many failure modes that would show up as multi-bit errors and a 'parity bit' would not cover these.
Similarly the classic 72 bits to provide 64 bits plus ECC fails because a single cell failing can look like all of a cell's nine bits failing.

However some of the extended ECCs would work - 64-bytes of data plus ECC in 576 bits would work against even against a single-cell '9-bit' failure. And when dealing with a terabyte, 64 byte chunks are very reasonable.

RealScience
2 / 5 (1) Jul 11, 2014

Even at this scale, for chip fabrication an additional 25 cents per device is huge. This is a ton of gold. This is why many chip vendors have moved away from even occasional Au bonding.

Certainly the manufacturers will try to eliminate even 25 cents per device, but a terabyte flash drive now costs $1750 (msrp from Kingston), and even a terabyte hard disk is on the order of $50. In ten years 25 cents per terabyte might well make a difference in competing with hard disks, but even then it will not be huge in comparison to flash memory prices.

Of course the article does not give sufficient details to be sure - they could, for example, be stacking devices to reach that terabyte per postage stamp figure, and the precious metals cost could therefore be 8x higher.
DonGateley
5 / 5 (1) Jul 11, 2014
@RealScience: yes, you are absolutely right and I should have seen that myself.
EyeNStein
not rated yet Jul 14, 2014
The scale of the cells is unclear from the article or the graphics. The Top image depicts at least 300nm width of Au on top of a cell.
Their results may be for a test/prototype scale device. A realistic ~40nm fabrication scale device cell may alter the working voltage (2volts) and effects of porosity grain significantly.