Engineers build first sub-10-nm carbon nanotube transistor

Feb 01, 2012 by Lisa Zyga feature
9-nm CNT transistor with electron microscope images. Image credit: Franklin, et al. ©2012 American Chemical Society

(PhysOrg.com) -- Engineers have built the first carbon nanotube (CNT) transistor with a channel length below 10 nm, a size that is considered a requirement for computing technology in the next decade. Not only can the tiny transistor sufficiently control current, it does so significantly better than predicted by theory. It even outperforms the best competing silicon transistors at this scale, demonstrating a superior current density at a very low operating voltage.

The engineers, from the IBM T.J. Watson Research Center in Yorktown Heights, New York; ETH Zurich in Zurich, Switzerland; and Purdue University in West Lafayette, Indiana, have published their study on the first sub-10-nm CNT transistor in a recent issue of .

Many research groups are working on reducing the size of transistors in order to meet the requirements of future computing technology for smaller, denser . When today’s transistors (silicon metal-oxide-semiconductor field-effect transistors, or Si MOS-FETs) are shrunk, they lose their ability to effectively control electric current, a problem called short-channel effects. For this reason, researchers have been modifying the Si MOS-FET design in an attempt to make the transistor perform better at sub-10-nm gate lengths, but these devices still face performance challenges.

In the new study, the engineers have discarded silicon altogether and turned to single-walled CNTs. Due to their superior electrical properties and ultrathin (1-2-nm diameter) bodies, CNTs have been proposed as a replacement for silicon for several years. Their ultrathin bodies should allow CNTs to maintain gate control of the current in a transistor even at short channel lengths, potentially enabling them to avoid short-channel effects. The IBM team’s sub-10-nm CNT transistor is the first to demonstrate these advantages.

“The greatest significance of this work is in the demonstration that carbon nanotube transistors can not only perform well at sub-10-nm lengths, but that their performance is better than the best-reported Si-based transistors at similar lengths,” IBM researcher Aaron Franklin told PhysOrg.com. “For years it has been known that scaling bulk silicon devices would be extremely challenging, if not impossible, when lengths close in on 10-15 nm….The superb low voltage performance of this scaled carbon nanotube transistor is a sign post showing that there is a demonstrable alternative for extremely scaled transistors.”

Until the engineers built the sub-10-nm CNT transistor, no one knew that they would perform this well. Theories predicted that CNTs with ultrathin channels would experience a loss of gate control as well as a loss of drain current saturation in the output, both of which would degrade performance.

“The reason that theory projected a loss of gate control for nanotube transistors below 15 nm or so (despite their being extremely thin) is related to other unique transport physics for nanotube devices,” Franklin said. “Namely, the carrier effective masses (mass of electrons) are very small for nanotubes compared to other semiconductors, meaning they can tunnel or leak in the device more easily. This is one of the reasons that theories had suggested a loss of gate control, because these 'light' carriers would begin tunneling uncontrollably when the lengths became too small. In the paper, we show that the reason for this discrepancy is largely due to insufficient physics models for transport at the nanotube-metal contacts – previous models mostly ignore what could be happening with electrons getting through the metal-nanotube junction.”

When the engineers fabricated several individual transistors on the same nanotube, the smallest having a channel length of just 9 nm, they observed that the tiniest transistor exhibited superb switching behavior and drain current saturation, defying predictions. When compared to the best-performing sub-10-nm Si transistors of varying designs and diameters, the 9-nm CNT transistor had a diameter-normalized of more than four times that of the best silicon transistor. And it exhibited this impressive current density at a low operating voltage (0.5 volts), which is important for reducing power consumption.

The researchers predict that theoretical models can be improved by focusing more on the transport between the metal contacts and CNT. They also think that the high-performing 9-nm CNT transistors demonstrate the potential for using CNT transistors in tomorrow’s .

“The chief implication is that carbon nanotubes are still worth consideration for a future scaled transistor technology,” Franklin said. “What is often not realized by those outside the field is that transistors are essentially the only non-silicon devices that have experimentally been shown to have promise in extremely scaled transistors. There are many devices promoted by theory, or demonstrated in larger device structures, but none have been able to show the level of research bench-top performance that nanotubes have. Now, that said, it should be noted that there are challenges ahead before anyone will see an integrated transistor solution from nanotubes. But, to date, nothing related to nanotube has been shown to be fundamentally impossible to solve, from placement of nanotubes in precise locations to the complete separation of metallic and semiconducting nanotubes.”

Explore further: Pinpoint laser heating creates a maelstrom of magnetic nanotextures

More information: Aaron D. Franklin, et al. “Sub-10 nm Carbon Nanotube Transistor.” Nano Letters. DOI: 10.1021/nl203701g

Journal reference: Nano Letters search and more info website

4.9 /5 (36 votes)

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Benni
3.6 / 5 (15) Feb 01, 2012
At only 0.5 volts with four times the amperage density. This is truly innovation at it's best. My hats off to my colleagues.

Only drawback is the rest of us electrical engineers are about to head back to the classroom to re-learn transistor theory ( night school here I come again, as much as I hate you).

This is micro-miniaturization beyond our wildest dreams. Right now I'm just trying to imagine the how much smaller the size of our electronic control modules can be that we presently install on our electrical generation eqipment.

Luv you guys at IBM........
eachus
3 / 5 (1) Feb 01, 2012
The problem with this technology--and it is huge--is that given the best fabrication tools available today, making a device with few billion transistors or so and no one transistor outside of spec is very, very tough. Hey, it is very tough with today's 28 nm* transistors. But I expect, at least at first, devices with nanotube transistors will cost more to fabricate than their silicon counterparts. Why do it then? We will return to an era where supercomputers have lower system costs even with these higher device costs. Eventually, nanotube parts will get cheaper than their silicon counterparts.

* I could spend the whole 1000 characters describing various ways of measuring transistor sizes. The industry prefers to use half-pitch, one half the minimum distance between two lines. Design engineers prefer to work with effective gate length (EGL). For most processes, EGL is on the order of 80% of the half pitch. But you can have transistors with different EGLs on the same die.
antialias_physorg
4.2 / 5 (5) Feb 01, 2012
Only drawback is the rest of us electrical engineers are about to head back to the classroom to re-learn transistor theory

We should be used to it by now. I remember that the stuff I learned at uni, and which was state of the art then, was already outdated the moment I was handed my diploma.

Luv you guys at IBM

They really do some spectacular things there (racetrack memory, millipede memory, this) ... but so few of it ever sees the light of day for the consumer. Somehow they dont seem to have the knack for capitalising on their own inventions any more.

At only 0.5 volts with four times the amperage density. This is truly innovation at it's best.

I think the real challenge will be to get this up to production size. I.e. to get billions of transistors without (m)any faults on a 'chip' at low cost (with an easy to set up process) and faster than the silicon production line does.
Sonhouse
4.5 / 5 (4) Feb 01, 2012
They will be clearly built with redundant circuits and re-routing techniques that will bypass bad parts which will inevitably show up at those tiny feature, where you are starting to count individual atoms. The main problem will be getting the carbon nanotubes made uniformly enough to be incorporated into these structures and physically getting all those billions of perfect nanotubes in the right places, and doing it fast enough for real production. I don't see that happening any time soon. It's one thing to make individual transistors in the lab (I would like to see a study of the highest frequencies these CNT transistors can manage) and going to a production line. With lower power consumption, 3 dimensional structures can be imagined and built, of course with its attendant problems to be solved also. I think it will take at least 15 years to get this technique to the real world, but when they do, the computers using this technology would probably be 100 times faster than any today.
antialias_physorg
5 / 5 (1) Feb 01, 2012
They will be clearly built with redundant circuits and re-routing techniques that will bypass bad parts

which will make the structure again bigger than the current technology using silicon (smart rerouting and redundancy is way more complicated than simply making arrays of transistors)
SurfAlbatross
not rated yet Feb 01, 2012
This is quite awesome. Hats off to IBM for being able to pull the rabbit out of the hat. Although, I think it unlikely that this will replace CMOS any time soon for a few reasons:
1. The resistance quantum of 12000 Ohms in quasi 1-D systems is difficult get around. Look at the drive current at -1V at the paper's website. Current production silicon has a drive current orders of magnitude higher than that. So, you'd need to array the CNTs and that will likely make area advantage non existent.
2. How do you make complimentary logic with a material that has a 0eV band gap? You'll be burning up quite a lot of power if not.
Cynical1
1 / 5 (1) Feb 02, 2012
IBM has been at the forefront of this kind of stuff since the invention of the transister. If anyone knows how to tweak it, they do...
Cynical1
1 / 5 (1) Feb 02, 2012
Read two articles farther down about inexpensive, simpler method for producing 1,2 and 3D nanorods. This is the kind of simultaneous research activities that needs to be tied more closely.
antialias_physorg
5 / 5 (2) Feb 02, 2012
Read two articles farther down

While the picture in that article shows 'ordered' behavior I don't think that is ordered enough.

I think there are some other ways to do this: I saw an article a while ago where nanorods were grown from extremely regularly placed seeds to a defined length at right angles to a substrate. If terminated by a few atoms of iron one could 'shock' bend them in a defined direction by applying a sudden magnetic field.

Another approach, which I read about on physorg a while back, used very regular virus structures to shape a 'mould' which gives the nanorods a defined/structured substrate to grow on.

The real problem will be the reluctance of the industry to invest in truly new production methods. They like to be very conservative when it comes to investing in stuff that could be obsolete/superceded in short order.
kaasinees
1.8 / 5 (5) Feb 02, 2012
They will be clearly built with redundant circuits and re-routing techniques that will bypass bad parts


They already do this by locking damaged cores and sell them at cheaper prices.
Build 512 CPU cores and disable the bad cores.

Anyway what happened to germanium? which showed promising properties at this scale.
antialias_physorg
not rated yet Feb 02, 2012
Anyway what happened to germanium?

Germanium is senitive to temperature changes. The temperature control you need is much more demanding than with silicon.

It's also not as abundantly available as silicon. If germanium were to be use on such a large scale as silicon currently is the prices would skyrocket.
Lurker2358
1.3 / 5 (4) Feb 02, 2012
it does so significantly better than predicted by theory


I couldn't help but LOL.

Graphene and CNT seem to get that a lot.

Just because something works on paper doesn't mean it works in reality.

Just because something doesn't work on paper doesn't mean it doesn't work in reality.

We should treat stuff like Relativity, DM, and DE, and other things in physical science and cosmology this way as well.
rawa1
1 / 5 (6) Feb 02, 2012
From practical purposes only scalable nanotechnologies are of practical significance. Until we have no idea, how to arrange nanotubes into 2D/3D arrays and how to address them these experiments are of theoretical significance only. For example, the production of CPU transistor by transistor would take years - not to say about reliability of the result. These experiments are serving as an Intel PR only.
antialias_physorg
5 / 5 (4) Feb 02, 2012
These experiments are serving as an Intel PR only

This is a science site. Not an industry/economics/commercial launch site.

If you object to people publishing experimental results on physorg then you should go somewhere else.
marraco
2.3 / 5 (3) Feb 02, 2012
The problem with nanotube is that they cannot be further miniaturized. They are an one-time trick.
rawa1
1 / 5 (3) Feb 02, 2012
This is a science site. Not an industry/economics/commercial launch site.
The problem of formally thinking people is, they tend to live in reality, which they're helping to fabricate. But the fact is, only minority of PhysOrg articles is dedicated to original scientific studies - the rest is just the info about various industry/economics/commercial launches. I'm not objecting the scientific significance of this study, I'm objecting the practical impact of it. My apology applies to confusion of Intel with IBM.
mtc123
2 / 5 (3) Feb 02, 2012
Potential for:
780 Gbytes per square inch.
1950 Tbytes per cubic inch.
A neuron is around 5 to 100 micro meters.
Average of 5000 of these transistors in the length of the average neuron but single walled nanotubes are only 2 nm in diameter.
Uh....Skynet?
antialias_physorg
5 / 5 (3) Feb 02, 2012
Average of 5000 of these transistors in the length of the average neuron

You need to model the connections between neurons - that's where the beef is at (not in the number of neurons themselves).

And each neuron can have up to 100000 connections.

So even with carbon nanotube transistors we're still off by 1-2 orders of magnitude.
rawa1
2 / 5 (4) Feb 02, 2012
So even with carbon nanotube transistors we're still off by 1-2 orders of magnitude.
You'll need probably some more transistors to provide necessary quantum noise redundancy - which renders the human brain as a quite optimized computational device with respect to informational density.
Jaeherys
5 / 5 (1) Feb 04, 2012
@antialias
Only very specific neurons can have tens of thousands of connections. The average number of connections in an adult brain 3x10^14.

My textbook says about 350 trillion but wiki is probably more up to date.
antialias_physorg
not rated yet Feb 04, 2012
Yep. But they're all at different 8and changing) strengths - which is something you can't capture with a single transistor. so the problem gets even worse.

Not saying we'll never beat the computational density of the brain - but we're not there quite yet.
SurfAlbatross
not rated yet Feb 05, 2012
we have no idea, how to arrange nanotubes into 2D/3D arrays

2D has been done by growing them on a certain direction of pure quartz crystal.
Lurker2358
1 / 5 (2) Feb 05, 2012
So even with carbon nanotube transistors we're still off by 1-2 orders of magnitude.


You design nano-processors with re-configurable nano-routers, each capable of making like 65000 connections.

Each nano-processor simulates a neuron, and the routers allow you to simulate synapses.

Additionally, you can design a classical computer with nano-detection devices, which I have called the "Spy," capable of "reading" the state of each of the processors and routers, which will allow you to image the state of the neural network to a database for backup. This would be useful for imaging one electronic neural net to another.

Conceptually, I proved a 100% self-referencial, re-imagable hybrid of an electronic neural net processor and a classical computer is possible, and outlined the basic concept of how to do it.

Once we get transistors on the scale this article is claiming, it should be possible to do it.

The operating frequency and signal propagation will dwarf our brains
antialias_physorg
5 / 5 (1) Feb 05, 2012
You design nano-processors with re-configurable nano-routers, each capable of making like 65000 connections.

Each nano-processor simulates a neuron, and the routers allow you to simulate synapses.

Yes. And each of those nanorouters AND connections COMBINED has to be as large as the ONE chip in the article above. It's great, but we're not there yet.

Additionally, you can design a classical computer with nano-detection devices, which I have called the "Spy," capable of "reading" the state of each of the processors and routers

Your 'spy' is completely superfluous. If it is a reprogarmmable router, then it's state can be read directly via software.

Conceptually, I proved a 100% self-referencial, re-imagable hybrid of an electronic neural net processor and a classical computer is possible, and outlined the basic concept of how to do it.

I think you should go back to hitting the CS and biology textbooks (or rather: begin to)
Lurker2358
1 / 5 (3) Feb 06, 2012
"Software" would not be sufficient for copying and re-imaging the state of a neural net, because neural nets don't work on software.

Your brain has no software.

This is why a hybrid computer would need a second, classical mechanism to record and modify the state of each connection in the neural net.

The reason this came up is because "science fiction" A.I. is NOT just a neural net. Commander Data and "The Doctor" in Star Trek aren't just neural net computers, they are idealized neural nets which are hybridized with classical computer memory, so that they have the best of both worlds. For example, they are regularly descrbied as having a "Neural net," yet they are able to modify their own programming to add functionality, which means that they actually must be hybrids.

This requires the neural net to have neural interfaces with the classical computer components, as opposed to classical buses, in addition to manual interfaces and all of it's normal sensory input.
antialias_physorg
5 / 5 (2) Feb 06, 2012
This is why a hybrid computer would need a second, classical mechanism to record and modify the state of each connection in the neural net.

Why? Current hardware implementations of neural networks do not require this. You can set the strengths of the interconnections individually. This technology has been around since the 1980s.
Though it has fallen somewhat out of favor because real (biological) neural networks have abilities which hardwired chips do not:
- plasticity (reconfiguration of connections - not just connections strengths)
- neurogenesis (adding new neurons (and removing old ones))
This requires the neural net to have neural interfaces with the classical computer components

You mean like the monitor you're sitting in fornt of? That, too, is an interface between computers and a biological neural net.
that_guy
3 / 5 (2) Feb 07, 2012
according to 18 billion articles on physorg, scientists/researchers have found thousands of ways to make superior transistors, using nanotubes, graphene, polymers, unicorn jizzle, etc.

Now that's certainly interesting and amazing, but honestly I don't really care anymore. I'm waiting for the first article that describes how easy it is to manufacture these new transistors by the billion.

It doesn't really even matter how small the transistors are, by the way (Except in consideration with a silicon like manufacturing process). consider that moore's law is rapidly failing as we speak.

If we had a cheap chip the size of a dinner plate, but is a magnitude better in performance, heat, and power over silicon, it would be far more useful than this BS.
that_guy
not rated yet Feb 07, 2012
and to tie into your neuron argument guys...It's a stupid argument.

A transistor is much smaller than a neuron, and also much much faster.

A neuron has far more capability and connections than a transistor.

They are fundamentally different. The only semi adequate way to compare them is on a total processing ability - which to even match a brain in an entire data center requires 6 to 7 orders of magnitude in improvement. (Far beyond improvements allowed from graphene/unicorn jizzard alone)

As for self awareness/consciousness of AI - That probably needs a specific structure (Neural), programming, quantum elements, and probably other things that we haven't the faintest clue about.
Callippo
1 / 5 (2) Feb 07, 2012
I'm waiting for the first article that describes how easy it is to manufacture these new transistors by the billion.
It was subject of my first comment in this thread too. The scalability is the key for practical applications of nanotechnologies. The basic research is too remoted from its practical applications, because we have huge over-employments in physics - so that physicists do care only about projects, which do provide them additional job places and grants. The ignorance of cold fusion is the top of iceberg from this perspective. Relevant: http://www.physor...ood.html
that_guy
not rated yet Feb 07, 2012
I'm waiting for the first article that describes how easy it is to manufacture these new transistors by the billion.
It was subject of my first comment in this thread too. The scalability is the key for practical applications of nanotechnologies. The basic research is too remoted from its practical applications, because we have huge over-employments in physics - so that physicists do care only about projects, which do provide them additional job places and grants. The ignorance of cold fusion is the top of iceberg from this perspective. Relevant: http://www.physor...ood.html

I can't say I agree with you about the physicists. I think the easy solution is to offer incentive to take research funds or grants to find more practical methods. Sort of like a "solutions bonus" beyond the research paycheck.
bonner
1 / 5 (1) Feb 18, 2012
my roomate's aunt makes $83/hr on the laptop. She has been without work for 8 months but last month her pay was $8682 just working on the laptop for a few hours. Read more on this site...Nuttyrich dot com
cdkeli
1 / 5 (1) Feb 22, 2012
CNT don't require trashing the planet for exotic earth metals right?

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