Universal transistor serves as a basis to perform any logic function

The researchers who designed the transistor, led by Walter M. Weber at Namlab gGmbH in Dresden, Germany, have published the new concept in a recent issue of Nano Letters.

“Synthetic nanowires are used to realize the proof-of-principle,” Weber told PhysOrg.com. “However, the concept is fully transferable to state-of-the-art CMOS silicon technology and can make use of self-aligned processes.”

The new transistor’s core consists of a single nanowire made of a metal-semiconductor-metal structure, which is embedded in a silicon dioxide shell. Electrons or holes flow from the source at one end of the nanowire through two gates to the drain at the other end of the nanowire. The two gates control the flow of electrons or holes in different ways. One gate selects the transistor type by choosing to use either electrons or holes, while the other gate controls the electrons or holes by tuning the nanowire’s conductance.

Using a gate to select p- or n-type configuration is quite different from conventional transistors. In conventional transistors, p- or n-type operation results from doping that occurs during the fabrication process, and cannot be changed once the transistor is made. In contrast, the reconfigurable transistor doesn’t use any doping. Instead, an external voltage applied to one gate can reconfigure the transistor type even during operation. The voltage causes the Schottky junction near the gate to block either electrons or holes from flowing through the device. So if electrons are blocked, holes can flow and the transistor is p-type. By applying a slightly different voltage, the reconfiguration can be switched again, without interfering with the flow.

The scientists explain that the key to making this reconfiguration work is the ability to tune the electronic transport across each of the two junctions (one per gate) separately. Their simulations showed that the current is dominated by tunneling, suggesting that the nanowire geometry plays an important role in the ability for independent junction control.

Because the reconfigurable transistor can perform the logic functions of both p- and n-type FETs, a single transistor could replace both a p- and n-type FET in a circuit, which would significantly reduce the size of the circuit without reducing functionality. Even at this early stage, the reconfigurable transistor shows very good electrical characteristics, including a record on/off ratio and reduced leakage current compared to conventional nanowire FETs. In the future, the researchers plan to further improve the transistor’s performance.

“We are varying the material combinations to further boost device performance,” Weber said. “Further on, first circuits implementing these devices are being built. … The biggest challenge will be to incorporate the extra gate signals in the cell layout allowing flexible interconnection to the other transistors.”

More information: André Heinzig, et al. “Reconfigurable Silicon Nanowire Transistors.” Nano Letters. DOI: 10.1021/nl203094h

Journal reference: Nano Letters

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