Imec implements multi-mode digital TV receiver on reconfigurable processor with record area efficiency

Digital broadcasting has recently gained a lot of interest, yet its deployment in products can be hampered by the many different regional standards that have been adopted world-wide. Due to the ultimate programmability, software-defined radio (SDR) solutions are becoming more and more attractive. Reconfigurable processor-based implementations allow saving on design-cost and time-to-market. However, SDR baseband solutions are traditionally reported to come with an area penalty when compared to ASIC counterparts. As area efficiency is one of the most important factors that determine the final cost of commercial chipsets, competitive area efficiency is crucial for SDR baseband solutions.

The instantiation of imec’s ADRES (architecture for dynamically reconfigurable embedded systems) processor was optimized by combining innovative algorithms (highly parallel implementation, software optimizations) with architecture improvements (optimized intrinsics, exploration towards leaner instance), resulting in a drastically smaller silicon area than the ASIC counterparts of the considered broadcasting standards. On top of its area efficiency, imec’s baseband processor proves to be highly flexible, supporting not only Digital TV standards (ATSC, ISDB-T, DVB-T,...) but also many other wireless communication standards: both an IEEE 802.11n inner receiver and a cat-4 LTE receiver can run real time on the same architecture.

Antoine Dejonghe, manager reconfigurable radio at imec, said: “We are delighted with these results, realized through our collaboration with Panasonic, that clearly prove the relevance and advantage of SDR baseband as a cost-efficient and flexible solution for consumer electronics.”

Provided by IMEC