Development of CMOS LSI technology for 100Gbit ethernet optical transceivers

May 19, 2011
Development of CMOS LSI technology for 100Gbit ethernet optical transceivers

Hitachi today announced the successful prototyping of a low-power CMOS gearbox LSI conforming with international standards, which was developed for optical transceivers as part of the effort to reduce power consumption in routers and network equipment to be used in the 100 gigabit (Gbit) Ethernet (henceforth, 100GbE). Optical receivers convert optical signals and electrical signals. The 100GbE CMOS gearbox LSI functions to convert the transmission rate and number of channels, converting the 4 channel × 25 gigabit per second (henceforth, Gb/s) electrical signals received from the network into 10 channels × 10Gb/s electrical signals which can be used within the equipment, and vice versa. Until now, a high-speed gearbox LSI based on SiGe process technology was used for this purpose, however, the achievement of a low-cost and low-power LSI based on the CMOS process was desired. The prototype 100 GbE gearbox LSI fabricated employs the four-phase clock circuit scheme using CMOS process technology, and achieves operation with a low power consumption of 2W, which is approximately one-quarter that of a SiGe gearbox LSI.

This work was partially supported by the "Universal Link" project of the National Institute of Information and Communications Technology (NICT), Japan.

Network traffic continues to dramatically increase each year with the rapid development of the broadband environment and the increasing use of high-definition video contents in this age of broadcast and communication convergence. As a result, the need exists for a communication network that provides both high speed and large capacity. In current internet communication, the Ethernet with a communication speed of 10Gb/s is widely used, however, to enable even higher speed, technology for a next generation 100GbE (10 times faster than the current level) was internationally standardized in June 2010. Today, technology development to conform with this standard is being conducted worldwide however a major issue of how to reduce the increasing power consumption which grows proportionally with increasing speed, remained.

Against this backdrop, Hitachi developed a prototype low-power CMOS gearbox LSI for optical transceivers used in routers and network equipment conforming with the 100GbE international standards. The technology developed includes the "four-phase clock circuit" which maintains the data processing speed of the LSI while reducing the circuit operating speed by 75%, and implementing this in the 25Gb/s interface circuit of the CMOS gearbox LSI. In addition, the CMOS interface (SerDes) circuit developed in 2010 by which has a low power consumption characteristic of 0.98mW per 1Gb/s, was employed in the prototype CMOS gearbox LSI.

Verification tests confirmed that the developed CMOS gearbox LSI operated with a power consumption of 2W; namely, a quarter that of a conventional SiGe gearbox LSI. The CMOS gearbox LSI developed can be applied to not only the 100GbE applications but also in signal transmission between LSIs in information-processing equipment such as servers and , and is expected to widely contribute to low power consumption of information-processing equipment.

These results will be presented at the International Solid-State Conference (ISSCC 2011), to be held from 20th to 24th February 2011 in San Francisco, U.S.

Details of circuit scheme developed
A four-phase-clock circuit scheme to realize lowpower consumption

In the receiving circuit of the 25Gb/s interface circuit, a circuit scheme that determines the level and phase of the received data by using four (phase) clocks with phase differences of 90 degrees, was applied. Through this approach, the interface is operated at a clock rate of 6.25GHz (a quarter of the bit rate) while maintaining the data-processing speed of the LSI, and power consumption is also reduced.

Development of CMOS LSI technology for 100Gbit ethernet optical transceivers

In addition, in a conventional receiving circuit, a receiving clock signal is generated by, first, distributing a high-speed 12.5GHz clock from a common PLL to four channels in the 25Gb/s interface circuit and then uses a phase-control circuit; a process consuming a large amount of power. A four-phase clock reducing this was achieved by placing a PLL in each channel of the receiving circuit, dispensing with the need for a power-hungry phase-control circuit. Further power conservation was achieved through this new circuit scheme by controlling the clock frequency allocated to each channel to a low-speed of 625MHz.

Explore further: Renesas announces SRAM using leading-edge 16 nm FinFET for automotive information systems

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