It's a wrap! Nanowire opens gate to new devices

Apr 07, 2011 By Bob Beale
A scanning electron micrograph of the horizontal wrap-gate nanowire transistor. Image courtesy of Adam Micolich.

(PhysOrg.com) -- In an interesting feat of nanoscale engineering, researchers at Lund University in Sweden and the University of New South Wales have made the first nanowire transistor featuring a concentric metal 'wrap-gate' that sits horizontally on a silicon substrate.

Two remarkable aspects of their design are the simplicity of the fabrication and the unique ability to tune the length of the wrap-gate via a single wet-etch step, notes Associate Professor Adam Micolich, an ARC Future Fellow in the Nanoelectronics Group in the UNSW School of Physics.

Packing ever higher densities of transistors into a comes at a hefty price – the reduced overlap between the semiconductor channel through which the current flows and the metal gate makes it harder to switch the current on and off.

This drove the development of the ‘Fin Field-Effect Transistor’, or FinFET, where the silicon either side of the channel is etched away to create a raised mesa structure. This allows the gate to fold down around the sides of the channel, improving the switching without increasing the chip space needed by the device. Even better control can be obtained by wrapping the gate all the way around the channel. But getting metal underneath the channel without compromising the device can be a formidable task using conventional ‘top-down’ silicon microfabrication techniques.

This has led to significant interest in self-assembled for computing applications (see D.K. Ferry, doi: 10.1126/science.1154446). These tiny semiconductor needles, around 50 nm in diameter and up to several microns in length, are grown using chemical vapour deposition and stand vertically on a semiconductor substrate, making it possible to deposit an insulator and gate metal around the nanowire’s entire outer surface.

Although these coated nanowires can be made into fully-functioning transistors in the vertical orientation, the process to achieve this is very involved. And in many cases, it is more desirable to have the nanowire transistor lying flat on the substrate, as with conventional silicon transistors. This poses an interesting challenge for nanotechnologists: Is it possible to make nanowire transistors with an all-around metal ‘wrap-gate’ that lay flat on a semiconductor substrate?

In work published this week in Nano Letters [Storm et al. doi:10.1021/nl104403g], the team not only demonstrate the first such horizontal wrap-gate nanowire , but they demonstrate that they can be made using a remarkably simple process that allows them to precisely set the wrap-gate’s length using a single wet-etch step, without any need for further lithography.

Their approach exploits the etchant solution’s ability to undercut the resist and etch along the nanowire, producing gates that range in length from slightly less than the contact separation to as low as 100 nm, simply by tuning the etchant concentration. The resulting devices have excellent electrical performance and can be produced reliably with high yield.

Beyond being a significant advance in nanofabrication techniques, these devices open interesting new avenues for fundamental research.

The wrap-gated nanowires are ideal for studies of one-dimensional quantum transport in semiconductors, where remarkable phenomena such as electron crystallization and spin-charge separation may be observed. Additionally, the strong gate-channel coupling combined with an exposed gold wrap-gate surface offers interesting potential for sensing applications by utilising the established chemistry for binding antibodies and other polypeptides to gold surfaces.

Explore further: A new dimension for integrated circuits: 3-D nanomagnetic logic

Related Stories

IMEC to create solutions for sub-45nm CMOS scaling

Jun 17, 2005

Together with its CMOS core partners, IMEC will announce several research breakthroughs on new gate-stack technologies and multiple-gate FET (MuGFET) devices at the 2005 Symposium on VLSI Technology. A combination of advances ...

Intel Researchers Improve Tri-Gate Transistor

Jun 13, 2006

Intel Corporation researchers today disclosed they have developed new technology designed to enable next era in energy-efficient performance. Intel's research and development involving new types of transistors ...

Recommended for you

Ultrafast remote switching of light emission

52 minutes ago

Researchers from Eindhoven University of Technology can now for the first time remotely control a miniature light source at timescales of 200 trillionth of a second. They published the results on Sept. 2014 ...

Nanotube cathode beats large, pricey laser

7 hours ago

Scientists are a step closer to building an intense electron beam source without a laser. Using the High-Brightness Electron Source Lab at DOE's Fermi National Accelerator Laboratory, a team led by scientist ...

User comments : 5

Adjust slider to filter visible comments by rank

Display comments: newest first

Quantum_Conundrum
1 / 5 (3) Apr 07, 2011
100nm long and 50nm wide is pretty large compared to what we are already using: 24nm to 33nm...

Maybe I'm missing something...

SincerelyTwo
not rated yet Apr 07, 2011
100nm long and 50nm wide is pretty large compared to what we are already using: 24nm to 33nm...

Maybe I'm missing something...


I think your missing out on having read the article.

"Two remarkable aspects of their design are the simplicity of the fabrication and the unique ability to tune the length of the wrap-gate via a single wet-etch step."
Quantum_Conundrum
1 / 5 (2) Apr 07, 2011
I think your missing out on having read the article.

"Two remarkable aspects of their design are the simplicity of the fabrication and the unique ability to tune the length of the wrap-gate via a single wet-etch step."


I read the article, they said they can tune the LENGTH, but gave no anticipated range of sizes other than the 100nm figure. Further, they said nothing about the width.

So how small can they go with this technique? Maybe they can do 10nm x 50nm?

Moreover, upon reading that section again, it says, "As low as 100nm," which means that it isn't even a sub-100nm process.

This is not remarkable, since we're already using something 4 times smaller...
Tristan
5 / 5 (2) Apr 07, 2011
If you read the last paragraph it seems that they're suggesting that this advance is useful in terms of research aimed at quantum effects in semiconductors, rather than in chip manufacturing.
Adam_Micolich
5 / 5 (1) Apr 08, 2011
The point isn't to compete with existing CMOS computer technologies, its a battle that everyone knows can't be won. The point was to push the envelope in terms of making devices with nanowires, simply to see how far we could go with it. If in 5 years someone adapts this process to make sub-100nm gate structures that would be fantastic, but as physicists at least, that's perhaps less interesting to us than what we can discover that's truly new and different to anything seen before. Scaling is for engineers ;)