For years now, transistors have been getting smaller and smaller. Research conducted by Jan-Laurens van der Steen of the MESA+ Institute for Nanotechnology at University of Twente, The Netherlands, has shown that electrons in silicon which is less than ten nanometres thick take on unusual characteristics.
To gain a better understanding of these nano-scale characteristics, he has worked on an accurate model which will play a very important role in the micro-electronics industry. He will defend his thesis on April 1st 2011 at the Faculty of Electrical Engineering, Mathematics and Computer Science.
Moore's Law states that the number of transistors inside a chip will double every eighteen months. In order for this to happen, transistors need to become ever smaller. Jan-Laurens van der Steen's research at the University of Twente has been looking at what happens when silicon crystals thinner than ten nanometres are made, a scale which the industry will soon reach.
Van der Steen's research revealed that the characteristics of the material begin to change drastically, a phenomenon that is often encountered in nanotechnology. In silicon of this thickness, it turns out to be more difficult to move the free electrons around. It seems as if the electrons become heavier compared to thick silicon samples. The research also showed that the mean free path of the electrons - the distance which they can move before they bump into something - gets shorter in thin silicon films.
In order to make use of these characteristics, it is important to be able to predict how nano-scale transistors will conduct electricity. Van der Steen has therefore developed a model which can explain these properties on both large and small scale structures. The model is known as a Single Scattering Model and is important for the development of the 11-nanometre CMOS generation and the even smaller generations to come.
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Van der Steen's thesis is entitled Geometrical Scaling Effects on Carrier Transport in Ultrathin-Body MOSFETs.