(PhysOrg.com) -- Watsons recent supercomputer victory over Jeopardys best players has some wondering if computers are getting smarter than, or at least as smart, as humans.
Garrett S. Rose, a Polytechnic Institute of NYU assistant professor of electrical and computer engineering, describes Watson as something similar to a giant search engine with the ability to mimic some behavior of the human mind. Because it depends on conventional computing hardware, he says, its ability to adapt and learn an ability that would make computer smarts more like human smarts is limited.
Dr. Rose is a member of an NYU-Poly research team that has created a technique for controlling circuits that process information similar to the way neural networks do.
Circuits in PCs have been designed to output exact results and for good reason, he says. They need to know that one plus one is two. Circuits used for artificial intelligence are different. They need to be able to fill in the gaps. They need to have plasticity like the brain does.
The research teams technique, which won the 24th IEEE International Symposium on VLSI Design Best Student Paper Award in January, helps circuits perform more reliably so they can fill in those gaps and carry out human-like functions recognizing voices and images, for example.
A key part of the technique is an algorithm that helps control the variations in memristors, nano-scale devices used in circuits for artificially intelligent hardware. Jeyavijayan Rajendran, a computer and electrical engineering PhD candidate, devised the algorithm, which the team presented in the award-winning paper, An Approach to Tolerate Process Related Variations in Memristor-Based Applications. Ramesh Karri, professor of electrical and computer engineering, and Harika Manem, also a computer and electrical engineering PhD candidate, co-authored the paper with Dr. Rose and Mr. Rajendran.
The team has been working with the Air Force Research Laboratory to develop its research and potential applications.
Explore further: Researchers parallelize a common data structure to work with multicore chips