ASM International and IMEC announce that they have demonstrated three generations of ASM’s Aurora® low-k and SiC dielectric barrier materials for IMEC’s 300mm pilot line.
These results have been established within the framework of the ASM - IMEC strategic partnership on Back-end-of-Line (BEOL) interconnect technology, which was announced on July 12, 2005. In this strategic partnership, IMEC and ASM will develop novel copper/low-k interconnects on 300mm wafers for application in chips of the nanotechnology era, with feature sizes of 45nm or less.
"The Aurora materials are known for their superior mechanical properties," comments Tominori Yoshida, ASM’s Business Unit Manager for PECVD. "Better mechanical properties, such as elastic modulus and hardness, and small pore size, usually makes materials more suitable for integration in a multi-layer interconnect and packaging", he continues. As with the first generation material, the next generations Aurora ultra low-k materials have also been demonstrated by IMEC to have excellent mechanical properties with, for example, an elastic modulus exceeding 9 GPa at a k value of 2.5, at a pore diameter less than 2nm.
These porous Extreme Low-k layers have been successfully patterned by IMEC with ArF immersion lithography into features suitable for 45nm to 32nm device interconnect wiring.
"We are pleased that we can offer our partners the low-k materials and technologies that they need, not only for our baseline interconnect process but also for advanced development for 45nm and 32nm technology. To this end, IMEC collaborates with leading equipment and materials suppliers worldwide to offer our IDM partners all possible options for future technology development" stated Luc Van den hove, IMEC’s Vice President Silicon Process and Device Technology.
As part of the continuing strategic partnership, IMEC and ASM will research multi-layer integrations of Aurora Extreme Low-k films (k<2.5) and the feasibility of even lower k-values, suitable for sub 32 nm technologies. ASM has installed two Eagle platforms in IMEC’s 300mm pilot line to provide low-k deposition capabilities for Aurora materials with k values ranging from about 3.0 to about 2.3, and SiC dielectric barrier layers with k values ranging from about 5.0 to about 3.8. This set of available materials spans multiple generations of low-k implementations down to the 22nm technology node.
Source: ASM Int.
Explore further: The brains behind the chip that works like a brain