Applied Materials, Inc. announced today that Taiwan Semiconductor Manufacturing Co. (TSMC) has qualified the Applied Centura Gate Stack system with DPN (decoupled plasma nitridation) technology for all of its 65nm-generation transistor fabrication processes. This advanced technology enabled TSMC to achieve their 65nm equivalent oxide thickness (EOT) scaling targets while increasing device speed.
Dr. Mong-Song Liang, senior director, Advanced Modules Technology Division, R&D, of TSMC, said, "Applied's single-wafer gate stack system has played a significant role in TSMC's leadership in advanced transistor fabrication. The gate stack system with Applied's DPN technology has helped us scale our transistors and extend oxynitride gate dielectrics to the 65nm generation, for both high performance and low-power applications, with the productivity needed for volume production. By combining Applied Materials' hardware and process technology expertise with TSMC's integration and manufacturing know-how, we were able to accelerate the implementation of this advanced gate stack technology, demonstrating the value of our strong relationship with Applied."
The Applied Gate Stack system provides excellent film interface control by integrating DPN, Radiance RTP, In Situ Steam Generation (ISSG) oxidation and polysilicon deposition processes on the Centura platform. TSMC already uses the 300mm Applied Centura Gate Stack system in its fabs, where its advanced single-wafer technology and multi-process integration capabilities have made it tool of record for transistor manufacturing. Unlike other gate oxynitride techniques, Applied's DPN technology uses an advanced plasma source to create a low-energy plasma, which results in precise nitrogen profile control.
"TSMC is a world leader in high-performance transistor fabrication, and we are delighted to contribute to their extension of oxynitride gate dielectric technology to 65nm," said Dr. Randhir Thakur, group vice president and general manager of Applied Materials' Front End Products group. "Our unique, fully integrated approach to gate stack fabrication provides optimum drive current and minimum gate leakage and allows additional generations of scaling over other technologies. The Gate Stack system is part of our suite of RunFastStayCool solutions for boosting device performance in next-generation transistors."
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