FlipChip, NEC sign cross-license agreement for advanced wafer level packaging technology

April 21, 2005

FlipChip International and NEC Electronics today announced that the two companies have entered into an extensive patent cross-licensing agreement for advanced wafer level packaging, flip chip bumping, solder bump reinforcement and wafer applied underfill technologies. As part of the agreement, FlipChip International will license its wafer level packaging patents including Ultra CSP, Polymer Collar, and Spheron product types to NEC Electronics. NEC Electronics will license its redistribution wafer level packaging, solder bump reinforcement and wafer applied underfill patents to FlipChip International.

Wafer level packaging, a process whereby semiconductors are packaged on the wafer prior to dicing, offers significant advantages in form factor and weight that enable real chip-scale packaging (CSP). The two companies will apply these advanced packaging technologies to devices such as discrete components, logic, ASICs, microprocessors, flash memory and other next generation devices for applications in the mobile phone, digital still camera, automotive, PDA and other emerging markets.

Commenting on the agreement, Bob Forcier, President and CEO of FlipChip International, said, "We are very pleased to commence a cross licensing agreement with NEC Electronics for next generation flip chip and wafer level packaging, which provide substantial improvements in performance, lower costs and dramatic reductions in size compared to traditional packaging technologies. This agreement has a strong upside for both companies."

"FlipChip International is renowned for its wafer level packaging technologies, and we are confident that this cross-licensing agreement will be beneficial for both companies," said Satoshi Takabayashi, general manager, Packaging Engineering Division, NEC Electronics. "Intellectual property is essential to our business, and this agreement enables both companies to provide our respective customers with advanced wafer level packaging technologies for rapidly growing markets."

Explore further: Samsung Electronics Develops Wafer Level Package for Higher Chip Performance

Related Stories

Packaging and Assembly Services for MST/MEMS - Worldwide

August 5, 2004

The enablingMNT review on Packaging and Assembly Suppliers for MST/MEMS confirms that many of the small and medium sized enterprises often lack both the expertise and the infrastructure for full wafer level packaging Research ...

Recommended for you

Samsung to disable Note 7 phones in recall effort

December 9, 2016

Samsung announced Friday it would disable its Galaxy Note 7 smartphones in the US market to force remaining owners to stop using the devices, which were recalled for safety reasons.

Cow gene study shows why most clones fail

December 9, 2016

It has been 20 years since Dolly the sheep was successfully cloned in Scotland, but cloning mammals remains a challenge. A new study by researchers from the U.S. and France of gene expression in developing clones now shows ...

0 comments

Please sign in to add a comment. Registration is free, and takes less than a minute. Read more

Click here to reset your password.
Sign in to get notified via email when new comments are made.