TSMC Verifies Fully Functional 90 Nanometer Chips Using Immersion Lithography Tools

December 22, 2004

Findings Suggests Immersion is Nearly Ready For Production

Taiwan Semiconductor Manufacturing Company, said that it used immersion lithography tools to produce fully functional 90nm devices. The finding was presented in a keynote speech at the Cymer Lithography Symposium in Semicon Japan on December 1, predating a similar announcement.
TSMC's circuits represent the first data that immersion-based lithography systems are nearing production-ready status.

Dr. Burn J. Lin, senior director of TSMC's micropatterning division, reported in the December keynote speech that TSMC had fabricated electrically functioning 90nm SRAM chips using a 90nm-node-capable prototype immersion scanner from ASML. The wafer batch was split at ASML for both immersion and dry exposures at critical layer before metal. After developing the resist image, the wafers were sent back to TSMC to complete the fabrication steps.

Yield, device characteristics and defect levels were comparable for both dry and wet scanners. The yield-related depth of focus of the immersion scanner is almost twice that of the dry scanner.

"While some optimization may still be in order, we have promising results pointing to immersion lithography systems and tools capable of producing functional deep-submicron devices that will scale well below the 90nm node," said Dr. Lin. "The larger focal range is the most significant finding, because it suggests that immersion tools can safely image with better yield than previously anticipated. This finding can be extrapolated to infer even greater benefits at the 65nm node."

TSMC estimates that immersion lithography tools may be called upon for 65nm production and are the chosen candidates for 45nm production. TSMC began installing its first 65nm immersion lithography system in early November this year.

Explore further: TSMC Unveils Nexsys 65nm Process Technology Plans

Related Stories

TSMC Unveils Nexsys 65nm Process Technology Plans

May 3, 2005

Taiwan Semiconductor Manufacturing Company, unveiled its newest semiconductor manufacturing process today at a Technology Symposium attended by over 400 of the industry’s leading IC companies. First wafers are expected ...

IMEC reports major progress in EUV

July 14, 2008

IMEC reports functional 0.186µm2 32nm SRAM cells made with FinFETs from which the contact layer was successfully printed using ASML’s full field extreme ultraviolet (EUV) Alpha Demo Tool (ADT). Applied Materials, using ...

Improved Materials Dominate Chip Evolution

November 3, 2005

Material innovation has replaced scaling as the primary source of performance and feature improvements in leading-edge CMOS semiconductors, IBM technologist Paul Farrar, Jr. told attendees at the ISMI Symposium on Manufacturing ...

IMEC advancing state-of-the-art in FinFETs

June 13, 2007

At this week’s VLSI Symposium, IMEC presents significant progress in the manufacturability, circuit performance and reliability of FinFETs. The results advance FinFET process technology towards being a candidate for the ...

Recommended for you

Samsung to disable Note 7 phones in recall effort

December 9, 2016

Samsung announced Friday it would disable its Galaxy Note 7 smartphones in the US market to force remaining owners to stop using the devices, which were recalled for safety reasons.

0 comments

Please sign in to add a comment. Registration is free, and takes less than a minute. Read more

Click here to reset your password.
Sign in to get notified via email when new comments are made.